Negative Capacitance Vertical Dopingless TFET and Its Analog/RF Analysis Using Interface Trap Charges

IF 2.5 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-01-23 DOI:10.1109/TDMR.2025.3533004

Vibhash Choudhary;Sachin Agrawal;Manoj Kumar;Madhulika Verma

{"title":"Negative Capacitance Vertical Dopingless TFET and Its Analog/RF Analysis Using Interface Trap Charges","authors":"Vibhash Choudhary;Sachin Agrawal;Manoj Kumar;Madhulika Verma","doi":"10.1109/TDMR.2025.3533004","DOIUrl":null,"url":null,"abstract":"The increasing demand for low-power devices has developed a huge interest in the Tunnel Field-Effect Transistor (TFET). However, challenges such as low ON current (I<inline-formula> <tex-math>$_{\\text {ON}}$ </tex-math></inline-formula>) and random dopant fluctuations limit its demand. To address these limitations, this paper proposed a charge plasma based ferroelectric negative capacitance vertical dopingless TFET (NC-VDL-TFET). In the proposed device, initially, dielectric engineering and architectural modification are used to improve the ION. The simulation result shows that these modifications increased the ION by 16.13%. Afterwards, a silicon-doped HfO2 ferroelectric material is employed above the gate oxide, which results in further improvement of 96.63% in ION. The overall simulation results demonstrate a significant improvement in DC and analog/RF characteristics at a low voltage supply (V<inline-formula> <tex-math>$_{\\text {DS}} = 0.3$ </tex-math></inline-formula>V), making the proposed device a potential candidate for future integrated circuits. Further, a detailed investigation of interface trap charges (ITCs) on the proposed device is analysed for reliability purposes. The simulated results performed for Analog/RF analysis show the proposed device is immune towards the impact of ITCs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"163-172"},"PeriodicalIF":2.5000,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10851333/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

The increasing demand for low-power devices has developed a huge interest in the Tunnel Field-Effect Transistor (TFET). However, challenges such as low ON current (I

$_{\text {ON}}$

) and random dopant fluctuations limit its demand. To address these limitations, this paper proposed a charge plasma based ferroelectric negative capacitance vertical dopingless TFET (NC-VDL-TFET). In the proposed device, initially, dielectric engineering and architectural modification are used to improve the ION. The simulation result shows that these modifications increased the ION by 16.13%. Afterwards, a silicon-doped HfO2 ferroelectric material is employed above the gate oxide, which results in further improvement of 96.63% in ION. The overall simulation results demonstrate a significant improvement in DC and analog/RF characteristics at a low voltage supply (V

$_{\text {DS}} = 0.3$

V), making the proposed device a potential candidate for future integrated circuits. Further, a detailed investigation of interface trap charges (ITCs) on the proposed device is analysed for reliability purposes. The simulated results performed for Analog/RF analysis show the proposed device is immune towards the impact of ITCs.

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.