Negative Capacitance Vertical Dopingless TFET and Its Analog/RF Analysis Using Interface Trap Charges

IF 2.5 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-01-23 DOI:10.1109/TDMR.2025.3533004

Vibhash Choudhary;Sachin Agrawal;Manoj Kumar;Madhulika Verma

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引用次数: 0

Abstract

The increasing demand for low-power devices has developed a huge interest in the Tunnel Field-Effect Transistor (TFET). However, challenges such as low ON current (I

$_{\text {ON}}$

) and random dopant fluctuations limit its demand. To address these limitations, this paper proposed a charge plasma based ferroelectric negative capacitance vertical dopingless TFET (NC-VDL-TFET). In the proposed device, initially, dielectric engineering and architectural modification are used to improve the ION. The simulation result shows that these modifications increased the ION by 16.13%. Afterwards, a silicon-doped HfO2 ferroelectric material is employed above the gate oxide, which results in further improvement of 96.63% in ION. The overall simulation results demonstrate a significant improvement in DC and analog/RF characteristics at a low voltage supply (V

$_{\text {DS}} = 0.3$

V), making the proposed device a potential candidate for future integrated circuits. Further, a detailed investigation of interface trap charges (ITCs) on the proposed device is analysed for reliability purposes. The simulated results performed for Analog/RF analysis show the proposed device is immune towards the impact of ITCs.

查看原文本刊更多论文

负电容垂直无掺杂TFET及其基于界面陷阱电荷的模拟/射频分析

随着对低功耗器件需求的不断增长，人们对隧道场效应晶体管（TFET）产生了极大的兴趣。然而，诸如低导通电流（I $_{\text {ON}}$）和随机掺杂剂波动等挑战限制了其需求。为了解决这些限制，本文提出了一种基于电荷等离子体的铁电负电容垂直无掺杂TFET （NC-VDL-TFET）。在该装置中，首先采用介电工程和结构修改来改善离子。仿真结果表明，这些改进使离子浓度提高了16.13%。随后，在栅极氧化物上方加入掺杂硅的HfO2铁电材料，离子进一步提高了96.63%。整体仿真结果表明，在低电压电源（V $_{\text {DS}} = 0.3$ V）下，该器件的直流和模拟/RF特性显著改善，使其成为未来集成电路的潜在候选器件。此外，为了可靠性的目的，对拟议装置上的界面陷阱电荷（ITCs）进行了详细的调查分析。模拟/射频分析的模拟结果表明，所提出的器件不受ITCs的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.