A Gate-Level SER Estimation Tool With Event-Driven Dynamic Timing and SET Height Consideration

Abstract

Radiation-induced soft errors in Integrated Circuits (ICs) have always been a matter of great reliability concern. However, the ongoing shrinking of CMOS technology nodes, which results in high frequency, low power, and small area exacerbates the problem. Thus, accurate evaluation of the ICs’ vulnerability to such errors has become crucial, especially when a radiation-hardening process is developed. In this article, we present a gate-level Soft Error Rate (SER) estimation framework based on an event-driven approach that models the generated Single Event Transients (SETs) as event pairs that propagate through the circuit. Dynamic Timing Analysis (DTA) is performed to estimate SET arrival times at Flip-Flop (FF) inputs and detect a soft error. Moreover, our approach approximates the glitch height and considers the noise immunity thresholds of gates to evaluate potential SET electrical masking. Additionally, our event-driven framework enables accurate propagation of Single Event Multiple Transients (SEMTs), which have become commonplace in combinational circuits. Experimental evaluation on ISCAS ’89 benchmarks indicates that the proposed event-driven height-aware approach exhibits 21.06% more accurate SER estimation on average, compared to conventional graph-based techniques, with respect to SPICE simulation. F1 scores further strengthen the previous result, demonstrating an average improvement of 11.86%. In terms of failures in time, experimental results show that the graph-based approach overestimates SER by an average of 8558 and up to 16485 errors compared to the proposed method. Finally, our approach is used to effectively identify the most sensitive gates that could potentially be hardened in a SER mitigation scenario.