FPGA Assessment Methodology of Adverse X-Ray Effects on Secure Digital Circuits

Abstract

Recent research demonstrates the feasibility of X-ray attacks. Unlike traditional fault injection methods, X-rays offer precise spatial targeting because of their short wavelength and high penetration power. This allows attackers to selectively target specific regions within a device, from individual transistors to larger blocks. This necessitates a new perspective on hardening techniques, requiring designers to consider the impact of X-ray irradiation on both fault injection and power consumption. To address this challenge, the paper proposes a characterization flow that analyzes the differences in side-channel leakages of FPGA components and their susceptibility to increased leakage due to X-ray effects. Despite the fundamental differences between ASIC and FPGA layouts, they both share the characteristic of being MOS technology-based, which makes them both susceptible to TID effects. The simulation results strongly support the theory that X-rays can induce leakage currents, thereby amplifying the side-channel information leakage observed in our experiments on FPGAs. Furthermore, these results provide concrete evidence that different FPGA components exhibit varying susceptibility to X-ray-induced leakage. Our findings reveal a clear hierarchy of vulnerability, with interconnects being the most susceptible elements, followed by registers, and lastly, logic components (LUTs and MUXes). This differential vulnerability offers valuable information for designers of secure cryptographic circuits. By understanding how X-rays impact different components, hardening techniques can be strategically targeted to provide the most effective protection against both fault injection and side-channel leakage.