Mechanism and Quantitative Modeling of the SRAM Soft Error Induced by Space Electrostatic Discharge

IF 2.5 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-04 DOI:10.1109/TDMR.2024.3510716

R.-J. Yuan;Rui Chen;J.-W. Han;Y.-N. Liang;Z.-Y. Wang;H.-L. Yu

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Abstract

This study investigates the characteristics, sensitive regions, failure mechanism, and quantitative model of the SRAM soft errors caused by spacecraft charging-induced electrostatic discharge (SESD) in HSPICE simulations. The results revealed that ‘1-0’ bit upset was one of the main characteristics of the soft errors caused by the SESD. The SESD-sensitive regions were located at the sense amplifier (AMP) and the 6T bit-cell array, with the SESD injecting at the power supply nodes. The main failure mechanisms are the reduction in the voltage difference between the two output nodes of the AMP and the recoverable breakdown in the P-channel metal oxide semiconductor (PMOS) of the 6T-cell, which is induced by the SESD transients. The quantization calculation model of the soft error induced by SESD for SRAM was established via MATLAB according to its failure mechanism, which bridged the characteristics of the SESD transient with the SRAM soft error to quickly evaluate the SESD errors. In addition, the quantization model was preliminarily verified via SESD experiments.

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空间静电放电诱发SRAM软误差的机理及定量建模

在HSPICE仿真中，研究了航天器充电静电放电（SESD）引起的SRAM软误差的特征、敏感区域、失效机制和定量模型。结果表明，“1-0”位扰动是SESD软误差的主要特征之一。SESD敏感区位于感测放大器（AMP）和6T位单元阵列，SESD注入在电源节点。其主要失效机制是AMP两个输出节点之间电压差的减小和6t电池的p通道金属氧化物半导体（PMOS）的可恢复击穿，这是由SESD瞬态引起的。根据SRAM的失效机理，利用MATLAB建立了SESD软误差量化计算模型，将SESD瞬态特性与SRAM软误差联系起来，快速评估SESD误差。此外，通过SESD实验对量化模型进行了初步验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.