Jinkai Zhang;Yinghao Yang;Zhe Zhou;Zhicheng Hu;Xin Zhao;Liang Chang;Hang Lu;Xiaowei Li
{"title":"Trident: The Acceleration Architecture for High-Performance Private Set Intersection","authors":"Jinkai Zhang;Yinghao Yang;Zhe Zhou;Zhicheng Hu;Xin Zhao;Liang Chang;Hang Lu;Xiaowei Li","doi":"10.1109/TC.2024.3517738","DOIUrl":null,"url":null,"abstract":"Private Set Intersection (PSI) is imperative in discovering the properties of the same data owned by two competitive parties, without revealing anything else of their respective data asset. Existing PSI solutions such as APSI and ORI-PSI suffer from severe communication and computation overhead due to inefficient communication and FHE polynomial evaluation, which hinders their deployment in practice. This issue is evident in both the upper-level protocol and the lower-level hardware platform. In this paper, we propose a novel software/hardware co-design acceleration architecture for PSI, termed as “Trident”, which includes two tightly coupled segments: from the protocol perspective, we investigate existing bottlenecks and propose a new PSI protocol with significantly less communication and computation under the security guarantee; besides, we re-architect the hardware platform by designing a PSI-specific accelerator, implemented with both FPGA and ASIC, targeting the key operations in the proposed protocol. We build a real-world experimental environment with two instantiated parties to verify the acceleration architecture, and highlight the following results: (1) up to 130<inline-formula><tex-math>$\\boldsymbol{\\times}$</tex-math></inline-formula>/145<inline-formula><tex-math>$\\boldsymbol{\\times}$</tex-math></inline-formula> speedup for the computation of <i>receiver</i> and <i>sender</i> parties; (2) up to 37<inline-formula><tex-math>$\\boldsymbol{\\times}$</tex-math></inline-formula> reduction of communication overhead. (3) up to 93,651<inline-formula><tex-math>$\\boldsymbol{\\times}$</tex-math></inline-formula> and 74,326<inline-formula><tex-math>$\\boldsymbol{\\times}$</tex-math></inline-formula> higher energy efficiency over the CPU-based ORI-PSI and APSI, respectively.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"74 4","pages":"1152-1167"},"PeriodicalIF":3.6000,"publicationDate":"2024-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computers","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10807166/","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Private Set Intersection (PSI) is imperative in discovering the properties of the same data owned by two competitive parties, without revealing anything else of their respective data asset. Existing PSI solutions such as APSI and ORI-PSI suffer from severe communication and computation overhead due to inefficient communication and FHE polynomial evaluation, which hinders their deployment in practice. This issue is evident in both the upper-level protocol and the lower-level hardware platform. In this paper, we propose a novel software/hardware co-design acceleration architecture for PSI, termed as “Trident”, which includes two tightly coupled segments: from the protocol perspective, we investigate existing bottlenecks and propose a new PSI protocol with significantly less communication and computation under the security guarantee; besides, we re-architect the hardware platform by designing a PSI-specific accelerator, implemented with both FPGA and ASIC, targeting the key operations in the proposed protocol. We build a real-world experimental environment with two instantiated parties to verify the acceleration architecture, and highlight the following results: (1) up to 130$\boldsymbol{\times}$/145$\boldsymbol{\times}$ speedup for the computation of receiver and sender parties; (2) up to 37$\boldsymbol{\times}$ reduction of communication overhead. (3) up to 93,651$\boldsymbol{\times}$ and 74,326$\boldsymbol{\times}$ higher energy efficiency over the CPU-based ORI-PSI and APSI, respectively.
期刊介绍:
The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field. It publishes papers on research in areas of current interest to the readers. These areas include, but are not limited to, the following: a) computer organizations and architectures; b) operating systems, software systems, and communication protocols; c) real-time systems and embedded systems; d) digital devices, computer components, and interconnection networks; e) specification, design, prototyping, and testing methods and tools; f) performance, fault tolerance, reliability, security, and testability; g) case studies and experimental and theoretical evaluations; and h) new and important applications and trends.