Effect of DC Stress on Low-Frequency Noise Characteristics of W-Doped In2O3 BEOL Transistors

IF 2.9 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Omkar Phadke;Khandker Akif Aabrar;Gihun Choe;Yuan-Chun Luo;Sharadindu Gopal Kirtania;Asif Islam Khan;Suman Datta;Shimeng Yu
{"title":"Effect of DC Stress on Low-Frequency Noise Characteristics of W-Doped In2O3 BEOL Transistors","authors":"Omkar Phadke;Khandker Akif Aabrar;Gihun Choe;Yuan-Chun Luo;Sharadindu Gopal Kirtania;Asif Islam Khan;Suman Datta;Shimeng Yu","doi":"10.1109/TED.2025.3532234","DOIUrl":null,"url":null,"abstract":"In this article, we perform the low-frequency noise (LFN) characterization of back-end-of-line (BEOL) compatible transistors. Specifically, the noise performance of oxide channel (W-doped In2O3, or IWO) transistors with a dielectric gate (IWOMOSFET) and ferroelectric gate (IWO FeFET) is studied and compared. The objective of this study is to understand the impact of a ferroelectric gate on the device reliability under dc stress. The normalized noise power spectral density (<inline-formula> <tex-math>${S}_{I}/{I}_{D}^{\\,{2}}$ </tex-math></inline-formula>) value is extracted for a fresh device and stressed device. We find that a ferroelectric gate-stack induces <inline-formula> <tex-math>$3\\times $ </tex-math></inline-formula> more noise than a dielectric gate-stack. Further, the increase in post stress <inline-formula> <tex-math>${S}_{I}/{I}_{D}^{\\,{2}}$ </tex-math></inline-formula> for IWO FeFET is <inline-formula> <tex-math>$7.5\\times $ </tex-math></inline-formula> higher than that for IWO MOSFET under positive stress voltage, and negligible for both devices under negative stress voltage. We conclude that the stress induced by the same gate voltage in IWO FeFET is higher than that in IWO MOSFET is due to the electric field enhancement caused by polarization in the ferroelectric gate-stack, which leads to more defect generation under the stress.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1489-1493"},"PeriodicalIF":2.9000,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10856747/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

In this article, we perform the low-frequency noise (LFN) characterization of back-end-of-line (BEOL) compatible transistors. Specifically, the noise performance of oxide channel (W-doped In2O3, or IWO) transistors with a dielectric gate (IWOMOSFET) and ferroelectric gate (IWO FeFET) is studied and compared. The objective of this study is to understand the impact of a ferroelectric gate on the device reliability under dc stress. The normalized noise power spectral density ( ${S}_{I}/{I}_{D}^{\,{2}}$ ) value is extracted for a fresh device and stressed device. We find that a ferroelectric gate-stack induces $3\times $ more noise than a dielectric gate-stack. Further, the increase in post stress ${S}_{I}/{I}_{D}^{\,{2}}$ for IWO FeFET is $7.5\times $ higher than that for IWO MOSFET under positive stress voltage, and negligible for both devices under negative stress voltage. We conclude that the stress induced by the same gate voltage in IWO FeFET is higher than that in IWO MOSFET is due to the electric field enhancement caused by polarization in the ferroelectric gate-stack, which leads to more defect generation under the stress.
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来源期刊
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices 工程技术-工程:电子与电气
CiteScore
5.80
自引率
16.10%
发文量
937
审稿时长
3.8 months
期刊介绍: IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.
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