Design of GaN-on-Silicon Power-Rail ESD Clamp Circuit With Ultralow Leakage Current and Dynamic Timing-Voltage Detection Function

Abstract

A power-rail electrostatic discharge (ESD) clamp circuit for monolithic GaN-based integrated circuits (ICs) with ultralow leakage current and dynamic timing-voltage detection function was proposed, which has been successfully verified in a 0.5- $\mu $ m GaN-on-Si process. The standby leakage current is only 0.8 nA. With the voltage detection, the proposed ESD clamp circuit can only be triggered by ESD events, and cannot be falsely triggered during fast power-on conditions. The experimental results demonstrate that the human-body-model (HBM) ESD robustness of the proposed design can be achieved over 6 kV. The triggered voltage of the ESD clamp circuit is flexible by adjusting the number of diode-connected high electron mobility transistors (HEMTs), so it can be utilized in different voltage ratings of ${V}_{\textit {CC}}$ .