Toward Understanding the Positive Shift of Reverse Turn-on Voltage in the Third Quadrant Operation in Planar SiC Power MOSFETs After Avalanche Breakdown

IF 2.9 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Wei-Cheng Lin;Yu-Sheng Hsiao;Chen Sung;Chu Thị Bích Ngọc;Rustam Kumar;Pei-Jie Chang;Surya Elangovan;Sheng-Shiuan Yeh;Chia-Lung Hung;Yi-Kai Hsiao;Hao-Chung Kuo;Chang-Ching Tu;Tian-Li Wu
{"title":"Toward Understanding the Positive Shift of Reverse Turn-on Voltage in the Third Quadrant Operation in Planar SiC Power MOSFETs After Avalanche Breakdown","authors":"Wei-Cheng Lin;Yu-Sheng Hsiao;Chen Sung;Chu Thị Bích Ngọc;Rustam Kumar;Pei-Jie Chang;Surya Elangovan;Sheng-Shiuan Yeh;Chia-Lung Hung;Yi-Kai Hsiao;Hao-Chung Kuo;Chang-Ching Tu;Tian-Li Wu","doi":"10.1109/TED.2025.3536447","DOIUrl":null,"url":null,"abstract":"In this study, we explore the stability of third-quadrant characteristics in planar SiC power MOSFETs under high drain bias above the avalanche breakdown condition. By using experimental measurements and TCAD simulations, we analyze the mechanisms responsible for the positive shift of reverse turn-on voltage (<inline-formula> <tex-math>${V}_{\\text {rev}, \\text {on}}$ </tex-math></inline-formula>) during the third-quadrant operation. When the drain bias is increased from 1500 to 1620 V, obvious negative shifts in threshold voltage (<inline-formula> <tex-math>${V}_{\\text {TH}}$ </tex-math></inline-formula>) and positive shifts in <inline-formula> <tex-math>${V}_{\\text {rev}, \\text {on}}$ </tex-math></inline-formula> are observed. The TCAD simulations attribute these shifts to the impact ionization caused by the high electric field inside the p-well regions. Furthermore, with the inclusion of positive fixed charges as the hole traps in the gate oxide near the SiO2/SiC interface, the simulation results show positive shifts of <inline-formula> <tex-math>${V}_{\\text {rev}, \\text {on}}$ </tex-math></inline-formula> consistent with the experimental results. These findings suggest that hole trapping caused by high drain bias above the avalanche breakdown condition can affect the stability of third-quadrant operation in planar SiC power MOSFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1270-1275"},"PeriodicalIF":2.9000,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10884917/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

In this study, we explore the stability of third-quadrant characteristics in planar SiC power MOSFETs under high drain bias above the avalanche breakdown condition. By using experimental measurements and TCAD simulations, we analyze the mechanisms responsible for the positive shift of reverse turn-on voltage ( ${V}_{\text {rev}, \text {on}}$ ) during the third-quadrant operation. When the drain bias is increased from 1500 to 1620 V, obvious negative shifts in threshold voltage ( ${V}_{\text {TH}}$ ) and positive shifts in ${V}_{\text {rev}, \text {on}}$ are observed. The TCAD simulations attribute these shifts to the impact ionization caused by the high electric field inside the p-well regions. Furthermore, with the inclusion of positive fixed charges as the hole traps in the gate oxide near the SiO2/SiC interface, the simulation results show positive shifts of ${V}_{\text {rev}, \text {on}}$ consistent with the experimental results. These findings suggest that hole trapping caused by high drain bias above the avalanche breakdown condition can affect the stability of third-quadrant operation in planar SiC power MOSFETs.
对雪崩击穿后平面SiC功率mosfet第三象限工作中反向导通电压正位移的理解
在本研究中,我们探讨了雪崩击穿条件下高漏极偏压下平面SiC功率mosfet第三象限特性的稳定性。通过实验测量和TCAD仿真,我们分析了在第三象限运行过程中反向导通电压(${V}_{\text {rev}, \text {on}}$)正移的机制。当漏极偏置从1500 V增加到1620 V时,观察到阈值电压${V}_{\text {TH}}$出现明显的负偏移,而${V}_{\text {rev}、\text {on}}$出现明显的正偏移。TCAD模拟将这些变化归因于p阱区域内高电场引起的冲击电离。此外,在SiO2/SiC界面附近的栅极氧化物中加入正电荷作为空穴陷阱,模拟结果显示${V}_{\text {rev}, \text {on}}$的正位移与实验结果一致。这些发现表明,雪崩击穿条件下高漏极偏压引起的空穴捕获会影响平面SiC功率mosfet第三象限工作的稳定性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices 工程技术-工程:电子与电气
CiteScore
5.80
自引率
16.10%
发文量
937
审稿时长
3.8 months
期刊介绍: IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信