A 1.54 pJ/b 80 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas in 28-nm Bulk CMOS

Abstract

This work represents a 140 GHz wideband 2-D scalable phased array in 28-nm bulk CMOS technology. The chip integrates $2\times 2$ transceiving elements with on-chip antennas and a $\times 16$ LO multiplication chain in $2.115\times 2$ .115 mm2. The elements are forming an RF beamformer while keeping approximately half-wavelength spacing between the elements. The integrated antennas leverage substrate thinning and substrate mode cancellation to boost the array radiation efficiency. The system adopts a superheterodyne transceiver (TRX) architecture with 25 GHz IF center frequency. The proposed work achieves 1.54 pJ/b and 80 Gb/s over-the-air (OTA) using 16-QAM modulation scheme for the overall transmit-receive link. To the best of the authors’ knowledge, this work achieves the highest reported array-level OTA data rate while improving the energy efficiency (pJ/b) by approximately an order of magnitude compared to other D-band transceiver arrays.