Reliability analysis of the intricacies of interfacial trap charges in HD-VS-FeFinFET and its applicability as CMOS inverter

IF 1.6 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability Pub Date : 2025-02-05 DOI:10.1016/j.microrel.2025.115610

Kajal Verma , Rishu Chaujar

{"title":"Reliability analysis of the intricacies of interfacial trap charges in HD-VS-FeFinFET and its applicability as CMOS inverter","authors":"Kajal Verma , Rishu Chaujar","doi":"10.1016/j.microrel.2025.115610","DOIUrl":null,"url":null,"abstract":"<div><div>This paper investigates the impact of semiconductor-oxide interfacial trap charges (ITCs) on the performance of Si/SiGe strained hetero dielectric vertically stacked ferroelectric-based FinFET (HD-VS-FeFinFET), formed with the novel amalgamation of several advanced technologies. ITCs induced degradation is a major concern for device reliability, and this study examines the reliability of HD-VS-FeFinFET by analyzing: (1) temperature affectability on ITCs, (2) impact of varying ITC densities and polarities, and comparing the results with vertically stacked ferroelectric-based FinFET (VS-FeFinFET). Temperature affectability reveals that HD-VS-FeFinFET exhibits better reliability with less average variations against ITCs at all operating temperatures such as 10.65% in leakage current (I<math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math>) and 11.39% in output resistance (R<math><msub><mrow></mrow><mrow><mi>o</mi><mi>u</mi><mi>t</mi></mrow></msub></math>) at 300 K which further decreases to 8.13% in I<math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math> and 7.76% in R<math><msub><mrow></mrow><mrow><mi>o</mi><mi>u</mi><mi>t</mi></mrow></msub></math> at 400 K in contrast to huge variation shown by VS-FeFinFET like 82.05% in I<math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math> and 43.10% in R<math><msub><mrow></mrow><mrow><mi>o</mi><mi>u</mi><mi>t</mi></mrow></msub></math> at 300 K along with 59.35% in I<math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math> and 29.86% in R<math><msub><mrow></mrow><mrow><mi>o</mi><mi>u</mi><mi>t</mi></mrow></msub></math> at 400 K. Further, the analysis done at various ITCs densities and polarities reveals that, at higher donor trap charge density of 1013 cm−2, the device performance alters significantly for VS-FeFinFET with degradation in I<math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math> by 552 times in comparison to HD-VS-FeFinFET which degrades only by 2.52 times, thus making it more reliable under varying environmental conditions. Lastly, HD-VS-FeFinFET based CMOS inverter shows improved immunity towards ITCs with negligible variations at all operating temperatures, thus with reliable circuit-level operation, HD-VS-FeFinFET proves itself an ideal choice for advanced logic circuits and low-power electronic applications in dynamic environments.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115610"},"PeriodicalIF":1.6000,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S002627142500023X","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

This paper investigates the impact of semiconductor-oxide interfacial trap charges (ITCs) on the performance of Si/SiGe strained hetero dielectric vertically stacked ferroelectric-based FinFET (HD-VS-FeFinFET), formed with the novel amalgamation of several advanced technologies. ITCs induced degradation is a major concern for device reliability, and this study examines the reliability of HD-VS-FeFinFET by analyzing: (1) temperature affectability on ITCs, (2) impact of varying ITC densities and polarities, and comparing the results with vertically stacked ferroelectric-based FinFET (VS-FeFinFET). Temperature affectability reveals that HD-VS-FeFinFET exhibits better reliability with less average variations against ITCs at all operating temperatures such as 10.65% in leakage current (I

_{o f f}

) and 11.39% in output resistance (R

_{o u t}

) at 300 K which further decreases to 8.13% in I

_{o f f}

and 7.76% in R

_{o u t}

at 400 K in contrast to huge variation shown by VS-FeFinFET like 82.05% in I

_{o f f}

and 43.10% in R

_{o u t}

at 300 K along with 59.35% in I

_{o f f}

and 29.86% in R

_{o u t}

at 400 K. Further, the analysis done at various ITCs densities and polarities reveals that, at higher donor trap charge density of 10¹³ cm⁻², the device performance alters significantly for VS-FeFinFET with degradation in I

_{o f f}

by 552 times in comparison to HD-VS-FeFinFET which degrades only by 2.52 times, thus making it more reliable under varying environmental conditions. Lastly, HD-VS-FeFinFET based CMOS inverter shows improved immunity towards ITCs with negligible variations at all operating temperatures, thus with reliable circuit-level operation, HD-VS-FeFinFET proves itself an ideal choice for advanced logic circuits and low-power electronic applications in dynamic environments.

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来源期刊

Microelectronics Reliability 工程技术-工程：电子与电气

CiteScore

3.30

自引率

12.50%

发文量

342

审稿时长

68 days

期刊介绍： Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.