Pranay Vuppunutala;Xiaolu Zhu;Junyong Park;Keith B. Hardin;Zachary C. N. Kratzer;John T. Fessler;Biyao Zhao;Siqi Bai
{"title":"System-Level Application of the Z-Directed Component (ZDC) for Power Integrity","authors":"Pranay Vuppunutala;Xiaolu Zhu;Junyong Park;Keith B. Hardin;Zachary C. N. Kratzer;John T. Fessler;Biyao Zhao;Siqi Bai","doi":"10.1109/TSIPI.2025.3527436","DOIUrl":null,"url":null,"abstract":"The design of the power distribution network (PDN) involves the careful placement of several decoupling capacitors around the integrated circuits (ICs) to mitigate the noise inherent with switching. A new technology capacitor, <italic>Z</i>-directed component (ZDC), can target printed circuit board (PCB) component locations at the package balls of the IC through the PCB. A commercially available PCB PDN design, using a conventional surface mount technology (SMT) decoupling solution, was analyzed utilizing a commercially available simulation-based tool and validated by impedance measurements. The ZDC PDN performance in the system was predicted by substituting a ZDC capacitor model for selected SMT capacitors. The validation was carried out using two-port PDN measurements on the PCB. Finally, an equivalent circuit model is developed using cavity model and plane-pair partial element equivalent circuit techniques to represent the physics associated with current paths from all the decoupling capacitors to the IC. The simulation results from a commercial tool are corroborated with both the measurements and an equivalent circuit model. It is demonstrated that opting for ZDC as a decoupling solution can deliver significantly lower impedances as compared to the SMT solution for this design. Thus, the ZDC approach is a promising decoupling solution for future power integrity applications, enhancing the power integrity performance of the system, facilitating the use of cost-effective lower layer count PCBs for much higher speeds than adopting an SMT strategy.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"10-18"},"PeriodicalIF":0.0000,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Signal and Power Integrity","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10834543/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The design of the power distribution network (PDN) involves the careful placement of several decoupling capacitors around the integrated circuits (ICs) to mitigate the noise inherent with switching. A new technology capacitor, Z-directed component (ZDC), can target printed circuit board (PCB) component locations at the package balls of the IC through the PCB. A commercially available PCB PDN design, using a conventional surface mount technology (SMT) decoupling solution, was analyzed utilizing a commercially available simulation-based tool and validated by impedance measurements. The ZDC PDN performance in the system was predicted by substituting a ZDC capacitor model for selected SMT capacitors. The validation was carried out using two-port PDN measurements on the PCB. Finally, an equivalent circuit model is developed using cavity model and plane-pair partial element equivalent circuit techniques to represent the physics associated with current paths from all the decoupling capacitors to the IC. The simulation results from a commercial tool are corroborated with both the measurements and an equivalent circuit model. It is demonstrated that opting for ZDC as a decoupling solution can deliver significantly lower impedances as compared to the SMT solution for this design. Thus, the ZDC approach is a promising decoupling solution for future power integrity applications, enhancing the power integrity performance of the system, facilitating the use of cost-effective lower layer count PCBs for much higher speeds than adopting an SMT strategy.