PCB Layout-Based Spatiotemporal Graph Convolution Network for Anomaly Prediction in Solder Paste Printing

Abstract

Predicting solder paste printing anomaly on the printed circuit board (PCB) can improve first-pass yield and reduce rework costs. Considering the impact of the PCB layout on the quality of solder paste printing, we propose a PCB layout-based spatiotemporal graph convolution network, in which we construct a graph to model the spatial distribution of solder pads. Specifically, since the printing quality is related to the spatial distribution of the pads, we convert the PCB to a graph according to the Pearson correlation of the printing quality and then trim the edges of the graph with a correlation threshold to model the spatial distribution of solder pads. To model the time-varying physicochemical properties of the solder paste, normalize the production time, calculate the attention of the production time, and reconstruct the printing quality based on the attention. Then, we devise a weighted loss to improve the performance of predicted printing of defective products due to the scarcity of defective products. Ultimately, the predicted printing quality is compared with the inspection threshold to estimate the degree of anomaly. The proposed method is validated on six days of real solder paste printing data, improving the average $F1$ score by 0.057 and the average accuracy by 0.022 for three typical anomalous printing behaviors over two temporal prediction scales.