SRAM With Oxide Semiconductor Pull-Down Transistors on the Backside Enabling Full-Node PPA Improvement

IF 4.1 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Electron Device Letters Pub Date : 2024-11-15 DOI:10.1109/LED.2024.3498840

Tao Chou;Tzu-Yun Liu;Li-Kai Wang;Tsai-Yu Chung;Ching-Wang Yao;Hsin-Cheng Lin;C. W. Liu

引用次数: 0

Abstract

The 6T SRAM bitcell, consisting of four pFETs on the same tier and two oxide-semiconductor pull-down transistors stacked on the backside, can achieve 17% power reduction, 32% performance enhancement, and 42% area reduction as compared to one-tier SRAM bitcell. With the high strength ratio of the pass-gate transistors to the pull-down transistors, near-threshold-voltage write reduces the minimum operating voltage.

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来源期刊

IEEE Electron Device Letters 工程技术-工程：电子与电气

CiteScore

8.20

自引率

10.20%

发文量

551

审稿时长

1.4 months

期刊介绍： IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.