High Signal Integrity Interconnects Embedded With Metasurface for Far-End Crosstalk Reduction and High-Speed Data Transfer

Yingcong Zhang;Guoan Wang
{"title":"High Signal Integrity Interconnects Embedded With Metasurface for Far-End Crosstalk Reduction and High-Speed Data Transfer","authors":"Yingcong Zhang;Guoan Wang","doi":"10.1109/TSIPI.2024.3509800","DOIUrl":null,"url":null,"abstract":"This article proposes a novel structure of coupled line with embedded metasurface aimed at mitigating far-end crosstalk (FEXT) in high-speed data transmission. The square loop metasurface structure is implemented under the coupled line to increase the mutual capacitance between signal traces, thereby mitigating FEXT in the coupled line. The capacitance and the inductance matrices of both conventional coupled line and the proposed metasurface-embedded structure are extracted with numerical equations from the simulations and applied to the equivalent circuit model to comprehensively analyze and accurately evaluate the proposed structure. To validate the design efficacy of the proposed concept, prototypes of conventional and the proposed coupled line structure are implemented on a FR-4 printed circuit board, and their performance in both frequency domain and time domain are measured and compared. Compared to conventional coupled line, experimental results demonstrate that the proposed metasurface embedded coupled line structure significantly enhances the FEXT performance while ensuring robust high-speed signal propagation along the signal traces. Specifically, FEXT is reduced by 8.2 dB within the frequency range of 1–12 GHz, and with the largest improvement of 42.84 dB at 10.9 GHz. This superior FEXT performance coupled with ultra-low latency underscores the significant potential of the proposed metasurface embedded coupled line structure for application in miniaturized high-speed systems.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"212-218"},"PeriodicalIF":0.0000,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Signal and Power Integrity","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10772054/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

This article proposes a novel structure of coupled line with embedded metasurface aimed at mitigating far-end crosstalk (FEXT) in high-speed data transmission. The square loop metasurface structure is implemented under the coupled line to increase the mutual capacitance between signal traces, thereby mitigating FEXT in the coupled line. The capacitance and the inductance matrices of both conventional coupled line and the proposed metasurface-embedded structure are extracted with numerical equations from the simulations and applied to the equivalent circuit model to comprehensively analyze and accurately evaluate the proposed structure. To validate the design efficacy of the proposed concept, prototypes of conventional and the proposed coupled line structure are implemented on a FR-4 printed circuit board, and their performance in both frequency domain and time domain are measured and compared. Compared to conventional coupled line, experimental results demonstrate that the proposed metasurface embedded coupled line structure significantly enhances the FEXT performance while ensuring robust high-speed signal propagation along the signal traces. Specifically, FEXT is reduced by 8.2 dB within the frequency range of 1–12 GHz, and with the largest improvement of 42.84 dB at 10.9 GHz. This superior FEXT performance coupled with ultra-low latency underscores the significant potential of the proposed metasurface embedded coupled line structure for application in miniaturized high-speed systems.
用于远端串扰减少和高速数据传输的嵌入超表面的高信号完整性互连
本文提出了一种带有嵌入式元表面的新型耦合线路结构,旨在减轻高速数据传输中的远端串扰(FEXT)。耦合线下的方形环形元表面结构可增加信号线之间的相互电容,从而减轻耦合线中的 FEXT。通过数值方程从仿真中提取了传统耦合线路和建议的元表面嵌入结构的电容和电感矩阵,并将其应用于等效电路模型,从而全面分析和准确评估了建议的结构。为了验证所提概念的设计效果,在 FR-4 印刷电路板上实现了传统耦合线结构和所提耦合线结构的原型,并对它们在频域和时域的性能进行了测量和比较。实验结果表明,与传统耦合线路相比,所提出的元表面嵌入式耦合线路结构在确保信号沿信号迹线稳健高速传播的同时,显著提高了 FEXT 性能。具体来说,在 1-12 GHz 频率范围内,FEXT 降低了 8.2 dB,在 10.9 GHz 频率范围内,FEXT 的最大改善幅度为 42.84 dB。卓越的 FEXT 性能和超低的延迟凸显了所提出的元表面嵌入式耦合线路结构在小型化高速系统中的巨大应用潜力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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