Balanced Modular Addition for the Moduli Set $ \{2^{q},2^{q}\mp 1,2^{2q}+1\}${2q,2q∓1,22q+1} via Moduli-($ 2^{q}\mp \sqrt{-1}$2q∓-1) Adders

IF 3.6 2区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Ghassem Jaberipur;Elham Rahman;Jeong-A Lee
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引用次数: 0

Abstract

Moduli-set $ \mathbf{\tau}=\{2^{\boldsymbol{q}},2^{\boldsymbol{q}}\pm 1\}$ is often the base of choice for realization of digital computations via residue number systems. The optimum arithmetic performance in parallel residue channels, is generally achieved via equal bit-width residues (e.g., $ \boldsymbol{q}~ \mathbf{i}\mathbf{n}~ \mathbf{\tau}$ ) that usually leads to equal computation speed within all the residue channels. However, the commonly difficult and costly task of reverse conversion (RC) is often eased in the existence of conjugate moduli. For example, $ 2^{\boldsymbol{q}}\mp 1\in \mathbf{\tau}$ , lead to the efficient modulo-( $ 2^{2\boldsymbol{q}}-1$ ) addition, as the bulk of $ \mathbf{\tau}$ -RC, via the New-CRT reverse conversion method. Nevertheless, for additional dynamic range, $ \mathbf{\tau}$ is augmented with other moduli. In particular, $ \mathbf{\phi}=\mathbf{\tau}\cup \{2^{2\boldsymbol{q}}+1\}$ , leads to efficient RC, where the added modulo is conjugate with the product $ 2^{2\boldsymbol{q}}-1$ of $ 2^{\boldsymbol{q}}\mp 1\in \mathbf{\tau}$ . Therefore, the final step of $ \mathbf{\phi}$ -RC would be fast and low cost/power modulo-( $ 2^{4\boldsymbol{q}}-1$ ) addition. However, the $ 2\boldsymbol{q}$ -bit channel-width jeopardizes the existing delay-balance in $ \mathbf{\tau}$ . As a remedial solution, given that $ 2^{2\boldsymbol{q}}+1=\left(2^{\boldsymbol{q}}-\boldsymbol{j}\right)\left(2^{\boldsymbol{q}}+\boldsymbol{j}\right)$ , with $ \boldsymbol{j}=\sqrt{-1}$ , we design and implement modulo-( $ 2^{2\boldsymbol{q}}+1$ ) adders via two parallel $ \boldsymbol{q}$ -bit moduli-( $ 2^{\boldsymbol{q}}\mp \boldsymbol{j}$ ) adders. The analytical and synthesis based evaluations of the proposed modulo-( $ 2^{\boldsymbol{q}}\mp \boldsymbol{j}$ ) adders show that the delay-balance of $ \mathbf{\tau}$ is preserved with no cost overhead vs. $ \mathbf{\phi}$ . In particular, the binary-to-complex and complex-to-binary convertors are merely cost-free and immediate.
模集$ \{2^{q},2^{q}\mp 1,2,2^{2q}+1\}${2q,2q +1}通过模-($ 2^{q}\mp \sqrt{-1}$2q +1)加法器的平衡模加法
模集$ \mathbf{\tau}=\{2^{\boldsymbol{q}},2^{\boldsymbol{q}}\pm 1\}$通常是残数系统实现数字计算的基础选择。在并行剩余信道中,最佳的算法性能通常是通过等位宽剩余(例如$ \boldsymbol{q}~ \mathbf{i}\mathbf{n}~ \mathbf{\tau}$)来实现的,这通常会导致所有剩余信道内的计算速度相等。然而,在共轭模的存在下,反变换通常是一项困难而昂贵的任务。例如,$ 2^{\boldsymbol{q}}\mp 1\in \mathbf{\tau}$,导致有效模-($ 2^{2\boldsymbol{q}}-1$)的添加,作为$ \mathbf{\tau}$ - rc的主体,通过New-CRT反向转换方法。然而,对于额外的动态范围,$ \mathbf{\tau}$增加了其他模量。特别地,$ \mathbf{\phi}=\mathbf{\tau}\cup \{2^{2\boldsymbol{q}}+1\}$导致有效的RC,其中添加的模与$ 2^{\boldsymbol{q}}\mp 1\in \mathbf{\tau}$的乘积$ 2^{2\boldsymbol{q}}-1$共轭。因此,$ \mathbf{\phi}$ - rc的最后一步将是快速和低成本/功率模-($ 2^{4\boldsymbol{q}}-1$)添加。但是,$ 2\boldsymbol{q}$ -bit通道宽度危及$ \mathbf{\tau}$中现有的延迟平衡。作为补救解决方案,鉴于$ 2^{2\boldsymbol{q}}+1=\left(2^{\boldsymbol{q}}-\boldsymbol{j}\right)\left(2^{\boldsymbol{q}}+\boldsymbol{j}\right)$,使用$ \boldsymbol{j}=\sqrt{-1}$,我们通过两个并行$ \boldsymbol{q}$位模($ 2^{\boldsymbol{q}}\mp \boldsymbol{j}$)加法器设计和实现了模($ 2^{2\boldsymbol{q}}+1$)加法器。对所提出的模($ 2^{\boldsymbol{q}}\mp \boldsymbol{j}$)加法器的分析和综合评估表明,与$ \mathbf{\phi}$相比,$ \mathbf{\tau}$的延迟平衡没有成本开销。特别是,二进制到复数和复数到二进制的转换仅仅是无成本和即时的。
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来源期刊
IEEE Transactions on Computers
IEEE Transactions on Computers 工程技术-工程:电子与电气
CiteScore
6.60
自引率
5.40%
发文量
199
审稿时长
6.0 months
期刊介绍: The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field. It publishes papers on research in areas of current interest to the readers. These areas include, but are not limited to, the following: a) computer organizations and architectures; b) operating systems, software systems, and communication protocols; c) real-time systems and embedded systems; d) digital devices, computer components, and interconnection networks; e) specification, design, prototyping, and testing methods and tools; f) performance, fault tolerance, reliability, security, and testability; g) case studies and experimental and theoretical evaluations; and h) new and important applications and trends.
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