Gate Length Dependence of Bias Temperature Instabilities up to 400 °C in 4H-SiC CMOS Devices

Abstract

This letter reports the bias temperature instabilities (BTI) of 4H-SiC CMOS devices with different gate lengths (L) and gate widths (W) for integrated circuits at 400 °C for the first time. The result shows that the threshold voltage shift of p-channel MOSFETs is significantly higher than that of n-channel MOSFETs. More serious BTI degradation is observed in CMOS devices with shorter L, especially for p-channel MOSFETs. Additionally, higher gate leakage current density and charged interface traps density are also found in fresh devices with shorter L. Through the energy-band structure, the physical cause of difference in transistor sizes originates from the inhomogeneous channel carrier concentration and charged interface traps density caused by the source and drain diffusion regions.