Rapid On-Wafer Quality Screening of AlGaN/GaN Superlattice Castellated Field Effect Transistors Using Short-Term Stress and Electroluminescence

IF 4.1 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Bazila Parvez;Akhil S. Kumar;James W. Pomeroy;Matthew D. Smith;Robert S. Howell;Martin Kuball
{"title":"Rapid On-Wafer Quality Screening of AlGaN/GaN Superlattice Castellated Field Effect Transistors Using Short-Term Stress and Electroluminescence","authors":"Bazila Parvez;Akhil S. Kumar;James W. Pomeroy;Matthew D. Smith;Robert S. Howell;Martin Kuball","doi":"10.1109/LED.2024.3478073","DOIUrl":null,"url":null,"abstract":"A electroluminescence (EL) based methodology has been devised to screen AlGaN/GaN Super-Lattice Castellated Field Effect Transistors (SLCFETs). EL intensity captured during off-state stressing has been correlated with an increase in gate leakage current after stress. Two off-state constant-voltage stress conditions were used, both applied over a stress time (\n<inline-formula> <tex-math>${\\mathrm {t}}_{\\text {stress}}$ </tex-math></inline-formula>\n) of 90 seconds: (a) \n<inline-formula> <tex-math>${\\mathrm{V}}_{\\text {GS}} = -12$ </tex-math></inline-formula>\n V, \n<inline-formula> <tex-math>${\\mathrm{V}}_{\\text {DS}} = 12$ </tex-math></inline-formula>\n V, and (b) \n<inline-formula> <tex-math>${\\mathrm{V}}_{\\text {GS}} = -12$ </tex-math></inline-formula>\n V, \n<inline-formula> <tex-math>${\\mathrm{V}}_{\\text {DS}} = 14$ </tex-math></inline-formula>\n V. The integrated EL intensity was found to scale with the ratio of off-state gate leakage current before and after the stress. The results were verified using step-stress tests to find the breakdown voltage (BV) of the gate dielectric of the stressed devices. BV was again found to scale with the measured integrated EL intensity for both the stress conditions. The results show that a short duration off-state stress in conjunction with EL can be a beneficial tool for quick assessment of the quality of gate dielectric across the wafer without incurring any significant damage to the devices. This becomes especially useful for rapid on-wafer device screening during large-scale production.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 12","pages":"2503-2505"},"PeriodicalIF":4.1000,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10713387/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

A electroluminescence (EL) based methodology has been devised to screen AlGaN/GaN Super-Lattice Castellated Field Effect Transistors (SLCFETs). EL intensity captured during off-state stressing has been correlated with an increase in gate leakage current after stress. Two off-state constant-voltage stress conditions were used, both applied over a stress time ( ${\mathrm {t}}_{\text {stress}}$ ) of 90 seconds: (a) ${\mathrm{V}}_{\text {GS}} = -12$ V, ${\mathrm{V}}_{\text {DS}} = 12$ V, and (b) ${\mathrm{V}}_{\text {GS}} = -12$ V, ${\mathrm{V}}_{\text {DS}} = 14$ V. The integrated EL intensity was found to scale with the ratio of off-state gate leakage current before and after the stress. The results were verified using step-stress tests to find the breakdown voltage (BV) of the gate dielectric of the stressed devices. BV was again found to scale with the measured integrated EL intensity for both the stress conditions. The results show that a short duration off-state stress in conjunction with EL can be a beneficial tool for quick assessment of the quality of gate dielectric across the wafer without incurring any significant damage to the devices. This becomes especially useful for rapid on-wafer device screening during large-scale production.
求助全文
约1分钟内获得全文 求助全文
来源期刊
IEEE Electron Device Letters
IEEE Electron Device Letters 工程技术-工程:电子与电气
CiteScore
8.20
自引率
10.20%
发文量
551
审稿时长
1.4 months
期刊介绍: IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信