Torsional-via-Assisted Nanoelectromechanical Memory Switches

Abstract

Monolithic three-dimensional integrated CMOS-nanoelectromechanical (NEM) circuits are gaining traction owing to their high chip density and low power consumption. However, the low endurance of NEM memory switches presents a reliability challenge. In this study, a novel torsional-via-assisted NEM memory switch design is proposed and experimentally demonstrated. The design incorporates vertically connected via anchors to allow torsion, which alleviates the maximum stress on the beam by ~46 % compared to the conventional in-plane design. The measurement data confirm endurance improvement, which sets a new benchmark for nonvolatile NEM memory switches with an endurance cycle exceeding 4,000 times. Furthermore, it was experimentally discussed that the electrode-gap narrowing induced by repeated switching cycles allows for a lower average operation voltage.