Comparative analysis of capacitorless DRAM performance according to stacked junctionless gate-all-around structures

Abstract

The characteristic comparison of the capacitor-less DRAMs in the structural form variation is investigated. Based on the simulation results of the three basic structures, such as circular, square, and rectangular nanosheets, the gate length (L_g), channel thickness (T_si), and width of the nanosheet (W_si) are considered as the main factors in design and the characteristic variations are verified according to the junctionless (JL) gate-all-around (GAA) geometry factors. The channel thickness is a major factor that has a major influence on the sensing margin and the retention time, which are important characteristics of DRAM. The thinner the thickness, the more deteriorated the sensing margin is confirmed. Retention time is due to the influence of the electric field distribution of the JL GAA structure, resulting in differences in structure. Finally, the rectangular type nanosheet is implemented in the stacked structure. As the number of stacks increases, the effective channel width increases compared to the layout footprint. In addition, by stacking vertically, the area where holes can be stored increases. Therefore, the sensing margin tends to increase as the number of stacks increases. However, the difference in diffusion due to the difference in the initially stored hole density, the retention time deteriorates as the number of stacks increases.