Study on single-event burnout hardening with reduction of hole current density by top polysilicon diode of SOI LDMOS based on TCAD simulations

IF 1.6 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability Pub Date : 2024-11-17 DOI:10.1016/j.microrel.2024.115551

Wenze Niu, Hongli Dai, Luoxin Wang, Yuming Xue, Haitao Lyu, Jinjun Guo

{"title":"Study on single-event burnout hardening with reduction of hole current density by top polysilicon diode of SOI LDMOS based on TCAD simulations","authors":"Wenze Niu, Hongli Dai, Luoxin Wang, Yuming Xue, Haitao Lyu, Jinjun Guo","doi":"10.1016/j.microrel.2024.115551","DOIUrl":null,"url":null,"abstract":"<div><div>In this paper, a single-event burnout (SEB)-hardened design for silicon-on-insulator lateral double-diffused MOSFET (SOI LDMOS) with a top polysilicon PN-junction diode (PN-LDMOS) is presented. By analyzing the hole current density of the device at different time points after a heavy-ion event, it is found that the introduced top polysilicon diode structure can reduce the hole current flowing to the source remarkably at a certain time. Thus, the voltage drop between the emitter and base of the parasitic NPN bipolar junction transistor (BJT) inherent in the device structure is reduced, and the deep p+ structure provides a low resistance path for the holes. The combined effect of these two structures effectively suppresses the turn-on of parasitic BJT and significantly reduces the risk of SEB occurrence. Compared to the traditional LDMOS (C-LDMOS), at a LET of 0.2 pC/μm, the SEB trigger voltage (<em>V</em><sub>SEB</sub>) of PN-LDMOS is improved from 129 V to 200 V, and the safe operating area (SOA) ratio (<em>η</em>) is increased from 58.8 % to 80 %. And the combination of polysilicon diode and field plates also optimizes the surface electric field distribution, increasing the breakdown voltage from 219.4 V to 249.7 V.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115551"},"PeriodicalIF":1.6000,"publicationDate":"2024-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271424002312","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

In this paper, a single-event burnout (SEB)-hardened design for silicon-on-insulator lateral double-diffused MOSFET (SOI LDMOS) with a top polysilicon PN-junction diode (PN-LDMOS) is presented. By analyzing the hole current density of the device at different time points after a heavy-ion event, it is found that the introduced top polysilicon diode structure can reduce the hole current flowing to the source remarkably at a certain time. Thus, the voltage drop between the emitter and base of the parasitic NPN bipolar junction transistor (BJT) inherent in the device structure is reduced, and the deep p+ structure provides a low resistance path for the holes. The combined effect of these two structures effectively suppresses the turn-on of parasitic BJT and significantly reduces the risk of SEB occurrence. Compared to the traditional LDMOS (C-LDMOS), at a LET of 0.2 pC/μm, the SEB trigger voltage (V_SEB) of PN-LDMOS is improved from 129 V to 200 V, and the safe operating area (SOA) ratio (η) is increased from 58.8 % to 80 %. And the combination of polysilicon diode and field plates also optimizes the surface electric field distribution, increasing the breakdown voltage from 219.4 V to 249.7 V.

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基于 TCAD 仿真的 SOI LDMOS 顶部多晶硅二极管降低空穴电流密度的单次烧毁硬化研究

本文提出了一种具有顶部多晶硅 PN 结二极管（PN-LDMOS）的硅-绝缘体横向双扩散 MOSFET（SOI LDMOS）的单次烧毁（SEB）硬化设计。通过分析该器件在重离子事件发生后不同时间点的空穴电流密度，发现引入的顶部多晶硅二极管结构能在一定时间内显著降低流向源极的空穴电流。因此，该器件结构中固有的寄生 NPN 双极结型晶体管（BJT）发射极和基极之间的压降减小了，而深 p+ 结构则为空穴提供了一条低电阻路径。这两种结构的共同作用有效抑制了寄生 BJT 的导通，大大降低了发生 SEB 的风险。与传统的 LDMOS（C-LDMOS）相比，在 LET 为 0.2 pC/μm 时，PN-LDMOS 的 SEB 触发电压（VSEB）从 129 V 提高到 200 V，安全工作区（SOA）比（η）从 58.8 % 提高到 80 %。多晶硅二极管和场板的组合还优化了表面电场分布，将击穿电压从 219.4 V 提高到 249.7 V。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Reliability 工程技术-工程：电子与电气

CiteScore

3.30

自引率

12.50%

发文量

342

审稿时长

68 days

期刊介绍： Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.