High-Speed and Area-Efficient Serial IMPLY-Based Approximate Subtractor and Comparator for Image Processing and Neural Networks

IF 2.1 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Nandit Kaushik;B. Srinivasu
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引用次数: 0

Abstract

In-Memory-Computing (IMC) through memristive architectures has recently gained traction owing to their capacity to perform logic operations within a crossbar, optimizing both area and speed constraints. This paper introduces two approximate serial IMPLY-based subtractor designs, denoted as Serial IMPLY-based Approximate Subtractor Design-1 (SIASD-1), Serial IMPLY-based Approximate Subtractor Design-2 (SIASD-2), with potential applications in image processing and deep neural networks. The proposed designs are implemented in MAGIC topology for comparison, named as Serial MAGIC-based Approximate Subtractor Design-1 (SMASD-1) and Serial MAGIC-based Approximate Subtractor Design-2 (SMASD-2). Moreover, these proposed subtractor designs are extended to design magnitude comparators. IMPLY-based approximate designs improve the overall latency up to 1.67× with energy savings in the range of 17.4% to 40.3% while occupying the same number of memristors for SIASD-1 and an increase of 3 to 5 memristors for SIASD-2, compared to the best existing exact 8-bit serial IMPLY subtractor. SMASD-1 and SMASD-2 improve the latency up to 1.43×, and energy efficiency are up by 77.6% compared to other MAGIC-based exact designs. Additionally, as comparators, the SIASD-1 and SIASD-2 are up to 4.93× faster with energy reduction up to 79.7% compared to their IMPLY-based equivalents. Similarly, the SMASD-1 and SMASD-2 reduce the latency up to 62% with area savings of 77%, compared to MAGIC-based equivalent designs. Furthermore, the proposed subtractor designs undergo analysis in an image processing application called Motion Detection, while the comparators are evaluated in Max Pooling operations. With Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) serving as assessment metrics, the proposed designs consistently demonstrate acceptable PSNR and SSIM values, affirming their suitability for these applications.
用于图像处理和神经网络的基于 IMPLY 的高速、高面积效率串行近似减法器和比较器
最近,通过忆阻器架构实现的内存计算(IMC)受到越来越多的关注,这是因为忆阻器架构能够在交叉条内执行逻辑运算,优化了面积和速度限制。本文介绍了两种基于 IMPLY 的近似串行减法器设计,分别称为基于 IMPLY 的近似串行减法器设计-1(SIASD-1)和基于 IMPLY 的近似串行减法器设计-2(SIASD-2),有望应用于图像处理和深度神经网络。为便于比较,建议的设计以 MAGIC 拓扑实现,命名为基于串行 MAGIC 的近似减法器设计-1(SMASD-1)和基于串行 MAGIC 的近似减法器设计-2(SMASD-2)。此外,这些拟议的减法器设计还可扩展用于设计幅度比较器。与现有的最佳精确 8 位串行 IMPLY 减法器相比,基于 IMPLY 的近似设计在占用相同数量的忆阻器(SIASD-1)和增加 3 到 5 个忆阻器(SIASD-2)的情况下,将总体延迟提高了 1.67 倍,节能范围在 17.4% 到 40.3% 之间。与其他基于 MAGIC 的精确设计相比,SMASD-1 和 SMASD-2 的延迟时间提高了 1.43 倍,能效提高了 77.6%。此外,作为比较器,SIASD-1 和 SIASD-2 与基于 IMPLY 的同类产品相比,速度提高了 4.93 倍,能耗降低了 79.7%。同样,与基于 MAGIC 的等效设计相比,SMASD-1 和 SMASD-2 的延迟时间缩短了 62%,面积节省了 77%。此外,还在名为 "运动检测 "的图像处理应用中对拟议的减法器设计进行了分析,并在最大池化操作中对比较器进行了评估。以峰值信噪比(PSNR)和结构相似性指数(SSIM)作为评估指标,所提出的设计始终显示出可接受的 PSNR 和 SSIM 值,从而肯定了它们在这些应用中的适用性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology 工程技术-材料科学:综合
CiteScore
4.80
自引率
8.30%
发文量
74
审稿时长
8.3 months
期刊介绍: The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.
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