Optimized Signal and Power Integrity of Silicon Interposer for HBM2E in CoWoS Packaging

Abstract

As high-speed digital systems require faster transmission and computing speed, the impact of complex interconnects in a limited space on the electrical performance of the channel-link system becomes more and more serious. This article aims to optimize the interconnection links between the enhanced second-generation high-bandwidth memory modules and systems on chip (CPU or GPU) for achieving the optimized signal and power integrity. Since the signal lines are susceptible to crosstalk, an improved diagonal-staggering wiring scheme is proposed to reduce the coupling coefficient between the signal lines by at least five times. The contour map for the mismatched systems with the peak distortion analysis is then applied to quickly find the optimal impedance design of lines for the best eye diagram. At a data rate of 6.4 Gb/s with a rise time of 15 ps, the eye height is optimized to be 4.6 times that in the original layout. Finally, the power supply and grounds are interleaved to increase the capacitance and alleviate the power noise through the power delivery network (PDN) in the construction of the four-element voltage regulator module along with the on-chip capacitor and the specific power–ground layers. Modifying the layout scheme in the PDN with reasonable decoupling capacitance can lead to an additional 1.4 times improvement in the eye height over the original design.