Solder joints stress analysis and optimization of chip component under shear and tensile load based on orthogonal experimental design and gray correlation analysis

IF 1.6 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability Pub Date : 2024-11-02 DOI:10.1016/j.microrel.2024.115529

Shuyi Li , Chunyue Huang , Xiaobin Liu , Gui Wang , Ying Liang , Chao Gao , Zhiqin Cao

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引用次数: 0

Abstract

The solder joint finite element analysis model of the 0201 chip component was established, by carrying out the shear loading and tensile loading finite element analysis respectively, the stress distribution pattern of the solder joint shear stress and tension stress were obtained. A solder joint stress measurement platform for the chip component was built, the solder joint stress measurement for the chip component under shear load was completed, and the accuracy of the simulation analysis results was verified. Selecting the solder joint volume, pad gap height, and pad length as design variables, and taking the maximum shear and tensile stress of the solder joint as the target, 16 groups of different parameter level combinations were designed by orthogonal test method, and combining with gray correlation analysis method, the bi-objective optimization design of shear and tensile stress of chip component solder joints was carried out—the optimal level combination of shear and tensile stress was obtained and verified by simulation. The results show that the influence ranking of maximum shear stress and tensile stress in solder joints of chip component are both pad gap height, pad length, and solder joint volume. The optimal parameter level combination is the solder joint volume of 0.0147mm

^{2}

, pad gap height of 0.05 mm, pad length of 0.35 mm, the maximum shear stress and the maximum tensile stress of the chip component solder joints increase by 44% and 23% respectively after the optimization, enhancing the shear strength and tensile strength of the solder joints in chip component simultaneously.

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基于正交实验设计和灰色关联分析的芯片组件在剪切和拉伸载荷下的焊点应力分析与优化

建立了 0201 芯片元件焊点有限元分析模型，分别进行了剪切加载和拉伸加载有限元分析，得到了焊点剪应力和拉应力的应力分布规律。搭建了芯片元件的焊点应力测量平台，完成了芯片元件在剪切载荷下的焊点应力测量，验证了仿真分析结果的准确性。选择焊点体积、焊盘间隙高度和焊盘长度为设计变量，以焊点最大剪切应力和拉伸应力为目标，采用正交试验法设计了 16 组不同参数水平组合，并结合灰色关联分析方法，对芯片元件焊点剪切应力和拉伸应力进行了双目标优化设计，得到了剪切应力和拉伸应力的最优水平组合，并进行了仿真验证。结果表明，芯片元件焊点最大剪切应力和拉伸应力的影响等级依次为焊盘间隙高度、焊盘长度和焊点体积。最佳参数水平组合为焊点体积 0.0147mm2、焊盘间隙高度 0.05 mm、焊盘长度 0.35 mm，优化后芯片元件焊点的最大剪切应力和最大拉伸应力分别提高了 44% 和 23%，芯片元件焊点的剪切强度和拉伸强度同时提高。

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来源期刊

Microelectronics Reliability 工程技术-工程：电子与电气

CiteScore

3.30

自引率

12.50%

发文量

342

审稿时长

68 days

期刊介绍： Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.