Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2024-10-22 DOI:10.1016/j.sse.2024.109012

Minsik Park , Minkyoung Seong , Jaeyong Jeong , Seungin Lee , Jonghyun Song , Hyoungho Ko , Ga-Won Lee , Woo-Suk Sul , Won-Chul Lee , Sanghyeon Kim , Jongwon Lee

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引用次数: 0

Abstract

In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).

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用于射频波段 III-V/Si 单片 3D 电路的硅基集成无源器件堆栈

在这项研究中，我们展示了一种基于硅（Si）的集成无源器件（IPD）堆栈，用于支持在射频（RF）频段工作的 III-V/Si 单片 3D (M3D) 集成电路。该 IPD 堆栈基于 8 英寸 CMOS 工艺线制造，并通过 M3D 与 InGaAs HEMT 层集成。为了同时最大限度地降低射频损耗和晶圆弯曲，在 IPD 中建立了富阱层和埋入氧化层的工艺条件。通过该工艺条件，共面波导在 30 GHz 时的射频损耗为 -0.631 dB/mm，低于 CMOS 代工厂的水平，而叠层的晶圆弯曲则低至 -5.5 μm。与迄今报道的在射频频段工作的其他基于 CMOS 代工工艺的电感器相比，电感器的最大品质因数显示出良好的数值。为了获得 IPD 叠层的压缩轮廓（这是将 III-V 有源层推进到晶圆到晶圆级 3D 粘合的最重要要求之一），开发了一种用于 IPD 最后 IMD 层的工艺方法，从而使 IPD 从拉伸轮廓变为压缩轮廓（相应的晶圆弯曲值从 -12.6 μm 到 +10.7 μm）。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.