Sputter-Deposited copper iodide thin film transistors with low Operating voltage

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2024-10-21 DOI:10.1016/j.sse.2024.109014

引用次数: 0

Abstract

This paper reports on a back-gated p-type thin film transistor (TFT) with copper iodide (CuI) as the channel material, a HfO₂ gate dielectric layer, and Al₂O₃ passivation. The γ-CuI channel was deposited from a CuI target using DC magnetron sputtering at room temperature. Our TFT can be fully shut off by V_G = 4 V, with a field-effect channel hole mobility μ_h ∼ 1.5–2 cm² V⁻¹ s⁻¹. An anneal in forming gas was performed twice, once at 200 °C, then at 250 °C to improve gate control, yielding a final I_on/I_off current ratio of ∼ 250. The anneal served two purposes: to reduce the oxygen acceptor density in the CuI channel and reduce the concentration of interface states between the CuI, Al₂O₃ passivation, and HfO₂. A model of the device was built in an industrial TCAD simulator, which reproduces the measured characteristics and allows an estimation of interface state densities and channel doping.

查看原文本刊更多论文

低工作电压的溅射沉积碘化铜薄膜晶体管

本文报告了一种以碘化铜（CuI）为沟道材料、HfO2 栅极电介质层和 Al2O3 钝化层的背栅 p 型薄膜晶体管（TFT）。γ-CuI沟道是在室温下利用直流磁控溅射技术从CuI靶上沉积下来的。我们的 TFT 可以在 VG = 4 V 时完全关闭，其场效应沟道空穴迁移率 μh ∼ 1.5-2 cm2 V-1 s-1。在成型气体中进行了两次退火，一次是在 200 ℃，另一次是在 250 ℃，以改善栅极控制，最终离子/关断电流比为 ∼ 250。退火有两个目的：降低 CuI 沟道中的氧受体密度；降低 CuI、Al2O3 钝化层和 HfO2 之间的界面态浓度。在工业 TCAD 模拟器中建立了该器件的模型，该模型再现了测量到的特性，并允许对界面态密度和沟道掺杂进行估计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.