A SEGR hardened trench gate DMOS with stepped source and optimized LOCOS structure

IF 1.6 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability Pub Date : 2024-10-21 DOI:10.1016/j.microrel.2024.115525

Yanfei Zhang , Xueqin Gong , Mengxin Liu , Xiaoxia Wen , Xiaowu Cai

{"title":"A SEGR hardened trench gate DMOS with stepped source and optimized LOCOS structure","authors":"Yanfei Zhang , Xueqin Gong , Mengxin Liu , Xiaoxia Wen , Xiaowu Cai","doi":"10.1016/j.microrel.2024.115525","DOIUrl":null,"url":null,"abstract":"<div><div>When irradiation experiment with heavy ions is carried out, Single-Event Gate Rupture (SEGR) is found for the conventional trench-gate DMOS (TG-DMOS) with LOCOS (Local Oxidation of Silicon). FIB analysis show that the failure spot is at the corner of the trench, which is the weakest point of the trench. In this paper, a SEGR hardened TG-DMOS with stepped source and optimized LOCOS structure is proposed. Stepped source is adopted to obtain a narrow base region and less voltage drop when the minority holes travel through the base region, which alleviates the electric field in the trench corner. Optimized LOCOS structure includes local oxidation area not only at the bottom of the gate trench but also at partial sidewall of the trench near the corner, protecting the trench corner and have no effect on the electrical characteristic. For the proposed structure, simulation shows that the peak electric field in the gate oxide is 3.8 MV/cm, which is almost half of the conventional TG-DMOS, and SEGR performance could be improved effectively.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115525"},"PeriodicalIF":1.6000,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271424002051","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

When irradiation experiment with heavy ions is carried out, Single-Event Gate Rupture (SEGR) is found for the conventional trench-gate DMOS (TG-DMOS) with LOCOS (Local Oxidation of Silicon). FIB analysis show that the failure spot is at the corner of the trench, which is the weakest point of the trench. In this paper, a SEGR hardened TG-DMOS with stepped source and optimized LOCOS structure is proposed. Stepped source is adopted to obtain a narrow base region and less voltage drop when the minority holes travel through the base region, which alleviates the electric field in the trench corner. Optimized LOCOS structure includes local oxidation area not only at the bottom of the gate trench but also at partial sidewall of the trench near the corner, protecting the trench corner and have no effect on the electrical characteristic. For the proposed structure, simulation shows that the peak electric field in the gate oxide is 3.8 MV/cm, which is almost half of the conventional TG-DMOS, and SEGR performance could be improved effectively.

查看原文本刊更多论文

具有阶跃源极和优化 LOCOS 结构的 SEGR 加硬沟道栅 DMOS

在用重离子进行辐照实验时，发现带有硅局部氧化（LOCOS）的传统沟槽栅DMOS（TG-DMOS）出现了单事件栅极破裂（SEGR）。FIB 分析表明，失效点位于沟道的拐角处，这是沟道的最薄弱点。本文提出了一种具有阶梯源和优化 LOCOS 结构的 SEGR 加硬 TG-DMOS 。采用阶跃源可以获得较窄的基底区，当少数空穴穿过基底区时，压降较小，从而减轻沟道角的电场。优化的 LOCOS 结构不仅包括栅极沟槽底部的局部氧化区，还包括沟槽靠近拐角处的部分侧壁，从而保护了沟槽拐角，并且对电气特性没有影响。仿真结果表明，对于所提出的结构，栅极氧化物中的峰值电场为 3.8 MV/cm，几乎是传统 TG-DMOS 的一半，SEGR 性能可以得到有效改善。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Microelectronics Reliability 工程技术-工程：电子与电气

CiteScore

3.30

自引率

12.50%

发文量

342

审稿时长

68 days

期刊介绍： Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.