Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part II: Adaptive Layer-Wise Refresh Technique

Abstract

Two-transistor-zero-capacitor (2T0C) DRAM cell has been proposed and extensively investigated as a memory device for processing-in-memory (PIM) applications. In this two-part article, we propose a novel vertical-transistor on the gate (VTG) 2T0C DRAM cell structure and the refresh technique for PIM applications and demonstrate their effectiveness. We described the improved retention characteristics of VTG DRAM in Part I. In Part II, we introduce the adaptive layer-wise refresh technique to minimize refresh energy consumption while maintaining the inference accuracy. Additionally, we developed a customized simulation framework to evaluate the inference accuracy and hardware performance of the 2T0C DRAM-based PIM macro. Through the simulations reflecting the device characteristics extracted in Part I, the layer-wise refresh technique can achieve the same inference accuracy of 92% and 91%, with refresh energy consumption reduced by 22.9% and 16% respectively, compared to the conventional refresh method.