Source-Drain Series Resistance Model for N-Stack Nanosheet FETs Using Transmission Line Matrix Method

Abstract

The continuous scaling of gate length as well as source and drain (S/D) area increases the parasitic S/D series resistance ${R}_{\text {sd}}$ and decreases the channel resistance ${R}_{\text {ch}}$ . As a result, the contribution of $R_{\text {sd}}$ to the total source-to-drain series resistance ${R}_{\text {tot}}$ increases, which decreases the percentage voltage drop across the channel. As a result, the drain drive current degrades at a higher gate bias. The increase in ${R}_{\text {sd}}$ increases power dissipation, thermal noise, and delay and reduces the maximum frequency of the device. Therefore, accurate models for ${R}_{\text {sd}}$ are needed for optimizing the device geometry to improve its performance and estimate the figure of merits, accurately. The analytical model for ${R}_{\text {sd}}$ in nanosheet FET (NSFET) to capture the impact of current distribution in different vertically stacked nanosheet (NS) channels is still elusive in the literature. To this end, we have developed an analytical model for ${R}_{\text {tot}}$ , which includes both ${R}_{\text {sd}}$ and ${R}_{\text {ch}}$ of the N-stack NSFETs, using the transmission line matrix (TLM) method for the first time. The TLM method effectively captures the effect of current distribution in the S/D region and each of the vertically stacked NS channels in N-stack NSFET. The results obtained from the developed model for ${R}_{\text {tot}}$ show good agreement with the simulation results validating the TLM method.