Bottom p-i-n Isolation Enabling GAA Nanosheet Transistor for Low-Power Applications

Abstract

A novel gate-all-around (GAA) nanosheet field-effect transistor (NSFET) with bottom p-i-n isolation is proposed for the first time, which can effectively suppress the parasitic subchannel leakage through introducing a reverse-biased p-i-n subtunnel FET (TFET) channel. By combining the advantages of GAA MOS channel and sub-TFET channel, the proposed NSFET with bottom p-i-n isolation scheme can reduce off leakage current to the same level as NSFET with full bottom dielectric isolation (BDI) scheme, exhibiting superior process compatibility and excellent immunity to process variations at the same time. Performance benchmarking in terms of both static power consumption and power delay product of bottom p-i-n NSFETs compared to full BDI NSFETs and PTS NSFETs has been carried out to assess the device performance for low-power operation.