A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation

Abstract

A fast-locking low-jitter hybrid frequency synthesizer using a charge-pump phase-locked loop (CP-PLL) and a multiplying delay-locked loop (MDLL) is presented. The CP-PLL uses a discriminator-aided detector (DAD) to alleviate the cycle-slipping issue and an auto-zero phase error compensator (AZ-PEC) to compensate the accumulated phase error during frequency acquisition to enhance the settling time. Then, the MDLL overcomes the jitter accumulation of CP-PLL. The synthesizer was fabricated in a 90-nm CMOS process. The output frequency ranges from 1 to 3 GHz. When switching from 1 to 2.5 GHz, the measured settling time using DAD and AZ-PEC is 520 ns, which is approximately 26 reference clock cycles. The power consumption is 12 mW at 2.5 GHz for a supply of 1.2 V. The integral root-mean-square jitter over 1 kHz–100 MHz is 1.62 ps.