Dual-Stripline Configuration for High-Density Routing in Chiplet Interconnects

Shekar Geedimatla;Jayaprakash Balachandran;Midhun Vysakham;Srinivas Venkataraman;Shalabh Gupta
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Abstract

Routing density is becoming in big challenge in die-to-die interconnects. In this article, we propose use of the dual-stripline configuration for routing signals in high-density interconnects. The scheme can improve the routing density by up to 33% when compared with the conventionally used stripline configuration. To address the challenges of crosstalk due to the proximity between vertically adjacent signal lines, half-pitch offset between lines on vertically adjacent layers has been proposed. The proposed routing scheme has been validated using 3-D full-wave electromagnetic simulations. The simulations show that the scheme can be used for increasing the routing density in the bunch-of-wires interface by 25%, while meeting all the bunch-of-wires channel specifications, which include eye-opening value above 68% unit interval at a bit error rate of $10^{-15}$ , with data rates of 16 Gbps per wire.
用于 Chiplet 互连中高密度路由的双干线配置
路由密度正成为芯片到芯片互连的一大挑战。在本文中,我们建议在高密度互连中使用双条线配置来路由信号。与传统的条纹线配置相比,该方案可将路由密度提高 33%。为了解决由于垂直相邻信号线之间距离过近而产生串扰的难题,我们提出了垂直相邻层上信号线之间半间距偏移的方案。我们利用三维全波电磁仿真验证了所提出的布线方案。仿真结果表明,该方案可用于将束线接口的路由密度提高 25%,同时满足所有束线信道规范,包括在误码率为 10^{-15}$ 的情况下,单位间隔值高于 68%,每条导线的数据传输速率为 16 Gbps。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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