Smart-CX – Method of extraction of parasitic capacitances in ICs

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2024-09-26 DOI:10.1016/j.sse.2024.109007

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引用次数: 0

Abstract

This paper proposes a novel rule-based parasitic capacitance extraction methodology, integrated into Smart-CX, to enhance the accuracy of SPICE simulations and physical verification of ICs. This methodology is crucial during the microchip design phase, particularly in preparation for fabrication on mature to advanced process nodes. The proposed enhanced analytical method addresses the accuracy/time tradeoffs between numerical and analytical extraction techniques. This study validates the accuracy of the methodology by comparison of the extracted parasitic parameters with foundry-provided 2D-models. The parasitic capacitances that are extracted within this method include: area capacitances

(C a)

, coupling capacitances (

C c)

, including via-to-via capacitances

(C m v)

, contact-to-gate capacitances

(C m g)

, contact-to-active capacitances (

C m c)

and fringe type capacitances with the top

(C f t)

and bottom

(C f b)

conductive layers.

查看原文本刊更多论文

Smart-CX - 集成电路寄生电容提取方法

本文提出了一种新颖的基于规则的寄生电容提取方法，并将其集成到 Smart-CX 中，以提高 SPICE 仿真和集成电路物理验证的准确性。这种方法在微芯片设计阶段至关重要，特别是在准备在成熟到先进工艺节点上制造时。所提出的增强型分析方法解决了数值提取技术和分析提取技术之间的精度/时间权衡问题。本研究通过将提取的寄生参数与代工厂提供的二维模型进行比较，验证了该方法的准确性。该方法提取的寄生电容包括：面积电容 (Ca)、耦合电容 (Cc)，包括通孔至通孔电容 (Cmv)、触点至栅极电容 (Cmg)、触点至有源电容 (Cmc) 以及顶层 (Cft) 和底层 (Cfb) 导电层的边缘型电容。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.