Understanding Bias Stress-Induced Instabilities in ALD-Deposited ZnO FeFETs Featuring HZO-Al2O3-HZO Ferroelectric Stack

IF 4.1 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Electron Device Letters Pub Date : 2024-09-18 DOI:10.1109/LED.2024.3462933

Chen Sun;Qiwen Kong;Gan Liu;Dong Zhang;Leming Jiao;Xiaolin Wang;Jishen Zhang;Haiwen Xu;Yang Feng;Rui Shao;Yue Chen;Xiao Gong

{"title":"Understanding Bias Stress-Induced Instabilities in ALD-Deposited ZnO FeFETs Featuring HZO-Al2O3-HZO Ferroelectric Stack","authors":"Chen Sun;Qiwen Kong;Gan Liu;Dong Zhang;Leming Jiao;Xiaolin Wang;Jishen Zhang;Haiwen Xu;Yang Feng;Rui Shao;Yue Chen;Xiao Gong","doi":"10.1109/LED.2024.3462933","DOIUrl":null,"url":null,"abstract":"In this work, we investigate the threshold voltage (\n<inline-formula> <tex-math>${V}_{\\text {TH}}\\text {)}$ </tex-math></inline-formula>\n and memory window (MW) dynamics under positive and negative bias stress (PBS/NBS) in atomic layer deposition (ALD)-grown zinc oxide (ZnO) ferroelectric field-effect transistors (FeFETs). The gate stack is engineered by inserting an Al2O3 layer between Zr-doped HfO2 (HZO) layers to form an HZO-Al2O3-HZO configuration. This enhances the MW of ZnO FeFETs to 1.75 V compared to devices without the Al2O3 insertion. From bias stress characterizations, notable results are obtained, especially under NBS conditions. It is revealed that the generation of disorder state (DS) O\n<inline-formula> <tex-math>$^{{2}-}$ </tex-math></inline-formula>\n defects plays a key role when devices are stressed by negative bias, leading to an abnormal positive shift in \n<inline-formula> <tex-math>${V}_{\\text {TH}}$ </tex-math></inline-formula>\n. Importantly, the degradation in MW caused by polarization pinning during NBS is mitigated by applying an even more negative bias. This can be explained by enhanced polarization erasing due to NBS. Our investigations provide a deep understanding of bias stress-induced instabilities in ALD-deposited ZnO FeFETs.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 11","pages":"2122-2125"},"PeriodicalIF":4.1000,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10683769/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

In this work, we investigate the threshold voltage (

${V}_{\text {TH}}\text {)}$

and memory window (MW) dynamics under positive and negative bias stress (PBS/NBS) in atomic layer deposition (ALD)-grown zinc oxide (ZnO) ferroelectric field-effect transistors (FeFETs). The gate stack is engineered by inserting an Al2O3 layer between Zr-doped HfO2 (HZO) layers to form an HZO-Al2O3-HZO configuration. This enhances the MW of ZnO FeFETs to 1.75 V compared to devices without the Al2O3 insertion. From bias stress characterizations, notable results are obtained, especially under NBS conditions. It is revealed that the generation of disorder state (DS) O

$^{{2}-}$

defects plays a key role when devices are stressed by negative bias, leading to an abnormal positive shift in

${V}_{\text {TH}}$

. Importantly, the degradation in MW caused by polarization pinning during NBS is mitigated by applying an even more negative bias. This can be explained by enhanced polarization erasing due to NBS. Our investigations provide a deep understanding of bias stress-induced instabilities in ALD-deposited ZnO FeFETs.

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了解采用 HZO-Al2O3-HZO 铁电叠层的 ALD 沉积氧化锌铁氧体场效应晶体管中由偏压引起的不稳定性

在这项工作中，我们研究了原子层沉积（ALD）生长的氧化锌（ZnO）铁电场效应晶体管（FeFET）在正负偏压（PBS/NBS）作用下的阈值电压（${V}_{text {TH}\text {）}$和存储窗口（MW）动态。）通过在掺杂 Zr 的 HfO2（HZO）层之间插入 Al2O3 层，形成 HZO-Al2O3-HZO 结构，从而设计了栅极堆栈。与未插入 Al2O3 的器件相比，这将 ZnO FeFET 的 MW 提高到 1.75 V。偏压应力特性分析取得了显著的结果，尤其是在 NBS 条件下。结果表明，当器件受到负偏压应力时，无序态（DS）O $^{{2}-}$ 缺陷的产生起到了关键作用，导致 ${V}_{text {TH}}$ 出现异常的正向移动。重要的是，在 NBS 期间，极化引脚导致的 MW 下降通过施加更负的偏压得到了缓解。这可以解释为 NBS 增强了极化擦除。我们的研究深入了解了 ALD 沉积氧化锌 FeFET 中偏压应力诱发的不稳定性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Electron Device Letters 工程技术-工程：电子与电气

CiteScore

8.20

自引率

10.20%

发文量

551

审稿时长

1.4 months

期刊介绍： IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.