Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

IF 2 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of the Electron Devices Society Pub Date : 2024-09-13 DOI:10.1109/jeds.2024.3459872

Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh

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使用神经紧凑建模方法分析应变对 3 纳米以下栅极全方位 CMOS 逻辑电路性能的影响

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来源期刊

IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology

CiteScore

5.20

自引率

4.30%

发文量

124

审稿时长

9 weeks

期刊介绍： The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.