CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
William Whitehead;Wonsik Oh;Luke Theogarajan
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Abstract

Intrinsically random hardware devices are increasingly attracting attention for their potential use in probabilistic computing architectures. One such device is the single-photon avalanche diode (SPAD) and an associated functional unit, the variable-rate SPAD circuit (VRSC), recently proposed by us as a source of randomness for sampling and annealing Ising and Potts models. This work develops a more advanced understanding of these VRSCs by introducing several VRSC design options and studying their tradeoffs as implemented in a 65-nm CMOS process. Each VRSC is composed of a SPAD and a processing circuit. Combinations of three different SPAD designs and three different types of processing circuits were evaluated on several metrics such as area, speed, and variability. Measured results from the SPAD design space show that even extremely small SPADs are suitable for probabilistic computing purposes, and that high dark count rates are not detrimental either, so SPADs for probabilistic computing are actually easier to integrate in standard CMOS processes. Results from the circuit design space show that the time-to-analog-based designs introduced in this work can produce highly exponential and analytical transfer functions, but that the less analytically tractable output of the previously proposed filter-based designs can achieve less variability in a smaller footprint. Probabilistic bits (P-bits) composed of the fabricated VRSCs achieve bit flip rates of 50 MHz and allow at least one order of magnitude of control over their simulated annealing temperature.
用于概率计算的 CMOS 单光子雪崩二极管电路
本征随机硬件设备因其在概率计算架构中的潜在用途而日益受到关注。单光子雪崩二极管(SPAD)和相关功能单元--可变速率 SPAD 电路(VRSC)就是这样一种设备,我们最近提出将其作为随机性来源,用于伊辛和波茨模型的采样和退火。本研究通过介绍几种 VRSC 设计方案,并研究在 65 纳米 CMOS 工艺中实现这些方案时的权衡,加深了对这些 VRSC 的理解。每个 VRSC 由一个 SPAD 和一个处理电路组成。对三种不同的 SPAD 设计和三种不同类型的处理电路的组合进行了面积、速度和可变性等指标的评估。SPAD 设计空间的测量结果表明,即使极小的 SPAD 也适用于概率计算,而且高暗计数率也不会对其造成损害,因此用于概率计算的 SPAD 实际上更容易集成到标准 CMOS 工艺中。电路设计空间的结果表明,本研究中引入的基于时间到模拟的设计可以产生高度指数化和分析性的传递函数,但之前提出的基于滤波器的设计的输出分析性较低,可以在较小的占位面积内实现较低的可变性。由制造的 VRSC 组成的概率位(P-bits)可实现 50 MHz 的位翻转率,并允许对其模拟退火温度进行至少一个数量级的控制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
5.00
自引率
4.20%
发文量
11
审稿时长
13 weeks
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