3-D Self-Aligned Stacked Ge Nanowires Complementary FET Featuring Single Gate Simple Process

Abstract

In this study, we experimentally demonstrated a state-of-the-art three-dimensional (3-D) self-aligned stacked hetero-oriented p-type Ge rectangle nanowire (NW) gate-all-around field-effect transistor (GAAFET) on n-type Ge diamond NW GAAFET of single-gate complementary FET (CFET). Anisotropic and isotropic dry etching processes are used to form the stacked NWs. Using Ge as the channel material with its optimal surface orientations of (111) for diamond NW nFET and (110) for rectangle NW pFET can enhance the device performance. The 3-D TCAD simulation indicates outperformance of the CFET device for 1-nm node applications. The proposed CFET structure can simplify the manufacturing technology and be fully compatible with current CMOS technology platform.