Over 50 mA Current in Interdigitated Diamond Field Effect Transistor

IF 4.1 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Damien Michez;Juliette Letellier;Imane Hammas;Julien Pernot;Nicolas Rouger
{"title":"Over 50 mA Current in Interdigitated Diamond Field Effect Transistor","authors":"Damien Michez;Juliette Letellier;Imane Hammas;Julien Pernot;Nicolas Rouger","doi":"10.1109/LED.2024.3453504","DOIUrl":null,"url":null,"abstract":"This letter presents the bulk diamond field-effect transistor (FET) with the highest current value reported at this moment on 3.5\n<inline-formula> <tex-math>$\\times $ </tex-math></inline-formula>\n3.5 mm2 Ib diamond substrate. The goal was to drastically increase the current of this type of device by increasing the total gate width thanks to an interdigitated architecture and homogeneous growth properties. The device develops a total gate width of 14.7 mm, with 24 paralleled fingers and a current higher than 50 mA at V \n<inline-formula> <tex-math>$_{\\text {DS}} = -15$ </tex-math></inline-formula>\n V and V \n<inline-formula> <tex-math>$_{\\text {GS}} =0$ </tex-math></inline-formula>\n V, at 450 K and under illumination. Its specific ON-resistance and threshold voltage are respectively 608 m \n<inline-formula> <tex-math>$\\Omega $ </tex-math></inline-formula>\n.cm2, 50 V. Resistivity of 3.6 m\n<inline-formula> <tex-math>$\\Omega $ </tex-math></inline-formula>\n.cm for a heavily boron-doped (p++)-diamond layer and \n<inline-formula> <tex-math>$1.52\\Omega \\cdot $ </tex-math></inline-formula>\ncm for a \n<inline-formula> <tex-math>$2.10^{{17}}$ </tex-math></inline-formula>\n cm−3 p-doped diamond layer were extracted at 450 K. This study indicates that it is possible to drastically improve the ON-state of FETs by using an interdigitated architecture, while using homogeneous large size diamond layers grown by CVD.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 11","pages":"2058-2061"},"PeriodicalIF":4.1000,"publicationDate":"2024-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10663906/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract

This letter presents the bulk diamond field-effect transistor (FET) with the highest current value reported at this moment on 3.5 $\times $ 3.5 mm2 Ib diamond substrate. The goal was to drastically increase the current of this type of device by increasing the total gate width thanks to an interdigitated architecture and homogeneous growth properties. The device develops a total gate width of 14.7 mm, with 24 paralleled fingers and a current higher than 50 mA at V $_{\text {DS}} = -15$ V and V $_{\text {GS}} =0$ V, at 450 K and under illumination. Its specific ON-resistance and threshold voltage are respectively 608 m $\Omega $ .cm2, 50 V. Resistivity of 3.6 m $\Omega $ .cm for a heavily boron-doped (p++)-diamond layer and $1.52\Omega \cdot $ cm for a $2.10^{{17}}$ cm−3 p-doped diamond layer were extracted at 450 K. This study indicates that it is possible to drastically improve the ON-state of FETs by using an interdigitated architecture, while using homogeneous large size diamond layers grown by CVD.
互嵌式金刚石场效应晶体管中的电流超过 50 mA
这篇文章介绍了目前报道的电流值最高的体金刚石场效应晶体管(FET),其基底为 3.5 美元/次的 3.5 mm2 Ib 金刚石。我们的目标是通过增加栅极总宽度来大幅提高此类器件的电流,这要归功于相互咬合的结构和均匀的生长特性。该器件的栅极总宽度为 14.7 mm,有 24 个并联指,在 450 K 和照明条件下,当 V $_{text\ {DS}} = -15$ V 和 V $_{text\ {GS}} =0$ V 时,电流高于 50 mA。其比导通电阻和阈值电压分别为 608 m $\Omega $ .cm2、50 V。在 450 K 时,重度掺硼(p++)金刚石层的电阻率为 3.6 m $\Omega $ .cm,2.10^{{17}}$ cm-3 p 掺杂金刚石层的电阻率为 1.52 $\Omega \cdot $ cm。这项研究表明,在使用通过 CVD 生长的均匀大尺寸金刚石层的同时,通过使用相互咬合的结构可以大幅改善场效应晶体管的导通状态。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Electron Device Letters
IEEE Electron Device Letters 工程技术-工程:电子与电气
CiteScore
8.20
自引率
10.20%
发文量
551
审稿时长
1.4 months
期刊介绍: IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.
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