Multi-Domain Dynamics and Ultimate Scalability of CMOS-Compatible FeFETs

IF 4.1 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Electron Device Letters Pub Date : 2024-09-05 DOI:10.1109/LED.2024.3454638

Nilesh Pandey;Yogesh Singh Chauhan;Leonard F. Register;Sanjay K. Banerjee

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引用次数: 0

Abstract

Recent research on CMOS-compatible FETs aims at aggressive scaling, targeting advanced performance nodes (7 nm - 14 nm), with the ultimate scalability limit posed by direct source-to-drain tunneling (DSDT). This letter investigates the impact of multi-domain dynamics in the ferroelectric gate dielectric on FeFET scalability. Coupled solutions of 2-D Poisson’s equation with the ferroelectric’s 2-D thermodynamics model (depolarizing energy + gradient energy + free energy) are the basis of a phase-field model. Varying ferroelectric and dielectric layer thicknesses can be used to engineer domain density. Minimal DSDT, maximum ON/OFF current ratio, and maximum memory window (MW) are possible when a single domain wall (domain density = 2) is located near the mid-channel. Additional domain walls increase DSDT. Furthermore, the drain electric field shifts the domain wall towards the source, increasing DSDT. Spatial gradient in polarization drastically impacts DSDT, with hard domain walls exhibiting lower DSDT due to increased polarization gradient. Our study predicts an optimal physical gate length of 12 nm (domain density = 2) with I

$_{\textit {ON}}$

$_{\textit {OFF}}~\sim ~{1}\times {10} ^{{6}}$

and subthreshold slope

$\sim ~100$

mV/dec.

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CMOS 兼容型 FeFET 的多域动力学和终极可扩展性

近期有关 CMOS 兼容型场效应晶体管的研究以先进的性能节点（7 纳米 - 14 纳米）为目标，积极进行扩展，最终的可扩展性限制是直接源极到漏极隧道效应（DSDT）。这封信研究了铁电栅极电介质中的多域动力学对 FeFET 可扩展性的影响。二维泊松方程与铁电二维热力学模型（去极化能 + 梯度能 + 自由能）的耦合解是相场模型的基础。不同的铁电层和介电层厚度可用于设计畴密度。当单个畴壁（畴密度 = 2）位于中通道附近时，可实现最小 DSDT、最大导通/关断电流比和最大存储窗口 (MW)。额外的畴壁会增加 DSDT。此外，漏极电场会将畴壁移向源极，从而增加 DSDT。极化的空间梯度对 DSDT 有很大影响，由于极化梯度增加，硬畴壁的 DSDT 更低。根据我们的研究预测，最佳物理栅极长度为 12 nm（畴密度 = 2），I $_{\textit {ON}}$ /I $_{\textit {OFF}}~\sim ~{1}\times {10}。^{{6}}$ 和阈下斜率 $\sim ~100$ mV/dec。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Electron Device Letters 工程技术-工程：电子与电气

CiteScore

8.20

自引率

10.20%

发文量

551

审稿时长

1.4 months

期刊介绍： IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.