Enhanced Fabrication and Assembly of 3-D Chiplets Based on Active Interposer With Frontside Via-Last TSVs

Abstract

The development of semiconductors, driven by artificial intelligence (AI) and fifth-generation technology (5G) technologies, has posed challenges in advanced packaging. To address these challenges, a 3-D packaging architecture based on active interposers has emerged. This article presents a novel fabrication method of the active interposer with high-aspect-ratio through-silicon vias (TSVs) and a reliable assembly process of 3-D chiplets. The proposed fabrication method of active interposer adopts frontside via-last TSV technology. First, a two-step protection method etching is implemented to address low-dielectric constant (DK) (low-k) material overetching risks. Then, baking at 350 °C after TSV etching is suggested to prevent short circuits. Last, a blade saw followed by laser scribing is proposed to mitigate die chipping during the dicing saw of low-k material. In addition, the 3-D chiplet assembly process is optimized for low thickness, large-area active interposer-to-substrate and high-density-I/O die-to-die bonding. Optimized recipe of thermal compression bonding (TCB), along with solder on pad (SoP), modified under-bump metallization (UBM), and novel flux transfer method, ensures high-quality solder joints without voids or bridging. The validity of the optimized assembly process is confirmed by reliability tests. The successfully integrated 3-D chiplets demonstrate that the fabrication process of the active interposer and the optimized assembly flow can enhance the performance and reliability of 3-D chiplet packaging in various applications.