Enhanced Junction Temperature Prediction Model for CoWoS Packaging With Multiple Chiplets

Abstract

With the development of high-performance computing and artificial intelligence, the transistor density of systems on a chip is also increasing exponentially, and the packaging solution for future high-performance chips has shifted toward chip-on-wafer-on-substrate (CoWoS) packaging. However, with the complexity of the CoWoS packaging structure and the increase in the number of chips, it is extremely challenging to analyze the steady-state heat of the CoWoS packaging. This is a necessary measure to optimize the chip layout and evaluate the package’s reliability. Based on the heat transfer path from the chip to the environment, an analytical model has been proposed in this study to calculate the temperature of multiple chiplets CoWoS packaging. The thermal coupling between multiple chiplets and the thermal equivalence of the through-silicon via (TSV) interposer are fully taken into account in this model. Each thermal resistance in the packaging has an analytical solution, and each chiplet has a junction temperature calculation expression. To verify the accuracy of the model calculation data, this study uses finite element simulation to calculate the chiplet temperature for two cases under two sets of thermal conditions. The data show that this model has high accuracy and fast calculation speed for temperature calculation of CoWoS multiple chiplet packaging.