Ziheng Wang;Xiaoshe Dong;Heng Chen;Yan Kang;Qiang Wang
{"title":"CUSPX: Efficient GPU Implementations of Post-Quantum Signature SPHINCS+","authors":"Ziheng Wang;Xiaoshe Dong;Heng Chen;Yan Kang;Qiang Wang","doi":"10.1109/TC.2024.3457736","DOIUrl":null,"url":null,"abstract":"Quantum computers pose a serious threat to existing cryptographic systems. While Post-Quantum Cryptography (PQC) offers resilience against quantum attacks, its performance limitations often hinder widespread adoption. Among the three National Institute of Standards and Technology (NIST)-selected general-purpose PQC schemes, SPHINCS\n<inline-formula><tex-math>${}^{+}$</tex-math></inline-formula>\n is particularly susceptible to these limitations. We introduce CUSPX (\n<u>CU</u>\nDA \n<u>SP</u>\nHIN\n<u>CS</u>\n \n<inline-formula><tex-math>${}^{+}$</tex-math></inline-formula>\n), the first large-scale parallel implementation of SPHINCS\n<inline-formula><tex-math>${}^{+}$</tex-math></inline-formula>\n capable of running across 10,000 cores. CUSPX leverages a novel three-level parallelism framework, applying it to \n<i>algorithmic parallelism</i>\n, \n<i>data parallelism</i>\n, and \n<i>hybrid parallelism</i>\n. Notably, CUSPX introduces parallel Merkle tree construction algorithms for arbitrary parallel scales and several load-balancing solutions, further enhancing performance. By treating tasks parallelism as the top level of parallelism, CUSPX provides a four-level parallel scheme that can run with any number of tasks. Evaluated on a single GeForce RTX 3090 using the SPHINCS\n<inline-formula><tex-math>${}^{+}$</tex-math></inline-formula>\n-SHA-256-128s-simple parameter set, CUSPX achieves a single task's signature generation latency of 0.67 ms, demonstrating a 5,105\n<inline-formula><tex-math>$\\times$</tex-math></inline-formula>\n speedup over a single-thread version and an 18.50\n<inline-formula><tex-math>$\\times$</tex-math></inline-formula>\n speedup over the previous fastest implementation.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"74 1","pages":"15-28"},"PeriodicalIF":3.6000,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computers","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10677363/","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Quantum computers pose a serious threat to existing cryptographic systems. While Post-Quantum Cryptography (PQC) offers resilience against quantum attacks, its performance limitations often hinder widespread adoption. Among the three National Institute of Standards and Technology (NIST)-selected general-purpose PQC schemes, SPHINCS
${}^{+}$
is particularly susceptible to these limitations. We introduce CUSPX (
CU
DA
SP
HIN
CS${}^{+}$
), the first large-scale parallel implementation of SPHINCS
${}^{+}$
capable of running across 10,000 cores. CUSPX leverages a novel three-level parallelism framework, applying it to
algorithmic parallelism
,
data parallelism
, and
hybrid parallelism
. Notably, CUSPX introduces parallel Merkle tree construction algorithms for arbitrary parallel scales and several load-balancing solutions, further enhancing performance. By treating tasks parallelism as the top level of parallelism, CUSPX provides a four-level parallel scheme that can run with any number of tasks. Evaluated on a single GeForce RTX 3090 using the SPHINCS
${}^{+}$
-SHA-256-128s-simple parameter set, CUSPX achieves a single task's signature generation latency of 0.67 ms, demonstrating a 5,105
$\times$
speedup over a single-thread version and an 18.50
$\times$
speedup over the previous fastest implementation.
期刊介绍:
The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field. It publishes papers on research in areas of current interest to the readers. These areas include, but are not limited to, the following: a) computer organizations and architectures; b) operating systems, software systems, and communication protocols; c) real-time systems and embedded systems; d) digital devices, computer components, and interconnection networks; e) specification, design, prototyping, and testing methods and tools; f) performance, fault tolerance, reliability, security, and testability; g) case studies and experimental and theoretical evaluations; and h) new and important applications and trends.