Design-Technology Co-Optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design

Abstract

A back-end-of-line (BEOL)-compatible stacked nanosheet tungsten doped indium oxide (IWO) n-type channel transistor is proposed for complementary logic gate operation with front-end-of-line (FEOL) p-type Si transistors. The proposed device structure ensures high on current density (Ion > 544 μA/μm) at V _GS = 1 V, compensating for lower electron mobility in IWO (than Si). A comprehensive process flow is proposed to prove its integration potential. A custom monolithic 3D (M3D) process-design-kit (PDK) and standard cell library are developed for design-technology co-optimization (DTCO), examining the power, performance, and area (PPA) trade-offs in representative integrated circuits with ∼ 0.8 million of gates. The Verilog-to-GDS synthesis results show a 47% average area reduction in M3D circuits while maintaining a similar energy-delay-product (EDP) compared to the conventional 2D circuits.