A 170-GHz Cascode Frequency Doubler With 15.6-dBm POUT in 130-nm SiGe BiCMOS

Abstract

In this letter, a two-way 170-GHz cascode frequency doubler with a delayed odd-harmonic cancellation line (DOHCL) for second-harmonic power and efficiency boosting fabricated in 130-nm SiGe BiCMOS technology is presented. The harmonic load pull is adopted to optimize the fundamental and second-harmonic impedances of the doubler core. The DOHCL converts the fundamental impedance from zero to optimum and temporarily holds the voltage swing at the load side at the cascode cores. Finally, the frequency doubler achieves a 3-dB bandwidth from 156 to 178 GHz and a bandwidth from 140 to 188 GHz for output power ( P _OUT ) ≥ 11 dBm. The maximum P _OUT and efficiency are 15.6 dBm and 12.1%, respectively, at 164 GHz. The chip area is 0.37 mm ² including pads. To the best of our knowledge, the proposed cascode frequency doubler achieves the highest P _OUT and power density in G -band Si-based frequency doublers.