Impact of the Scaling of LGS and LG on the On-State Breakdown Voltage of InAlN/GaN HFETs With Localized Fin Under the Gate Electrode

IF 2 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of the Electron Devices Society Pub Date : 2024-08-26 DOI:10.1109/JEDS.2024.3449798

Yatexu Patel;Pouya Valizadeh

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Abstract

In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the on-state breakdown voltage (BVon) of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. The results show that the downscaling of LGS and LG augments the electron velocity in the source-access region. Due to current conservation, the higher carrier velocity in the source-access region for the devices having shorter LGS and LG induces a higher electron density under the gated-channel. From what is theoretically observed, the presence of higher electron density close to the boundary with the velocity saturation region at the drain edge of the gate in devices having shorter LGS and LG does seem to initiate the device breakdown at lower drain voltages, leading to the deterioration of the on-state breakdown voltage.

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栅电极下有局部鳍片的 InAlN/GaN HFET 的 LGS 和 LG 缩放对通态击穿电压的影响

在本手稿中，我们研究了栅-源长度（LGS）和栅长度（LG）的缩放对金属面 InAlN/AlN/GaN 异质结构场效应晶体管（HFET）导通击穿电压（BVon）的影响。结果表明，LGS 和 LG 的缩减提高了源极-汲极区域的电子速度。由于电流守恒，LGS 和 LG 较短的器件在源极接入区的载流子速度较高，从而导致栅极沟道下的电子密度较高。从理论上观察，在 LGS 和 LG 较短的器件中，靠近栅极漏极边缘速度饱和区边界的较高电子密度似乎会在较低的漏极电压下引发器件击穿，从而导致导通击穿电压恶化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology

CiteScore

5.20

自引率

4.30%

发文量

124

审稿时长

9 weeks

期刊介绍： The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.