SOT-MRAM-Based Design for Energy-Efficient and Reliable Binary Neural Network Acceleration

Abstract

Binary neural networks (BNNs) are a highly promising option for realizing lightweight and efficient computing for applications on the edge. Spin-orbit torque MRAM (SOT-MRAM) has emerged as an attractive option for realizing fast and energy-efficient design. In this work, we propose a 4T-2R memory cell using viable and experimentally demonstrated SOT magnetic tunnel junction device (SOT-MTJ) for realizing highly energy-efficient XNOR operation (primary operation in BNNs). We also propose a pulse scheme to mitigate the inherent challenge of increased write error rate (WER) in SOT-MRAM device while achieving energy-efficient write. We perform 1000-point Monte Carlo (MC) simulations and demonstrate a bit error rate (BER) of 0.1– $5\times {10}^{-{3}}$ with extremely low energy consumption of ~4.8 fJ per XNOR operation. We also perform system-level simulations to show robustness of our cell by incorporating the asymmetric BERs resulting due to thermal noise and process variations (PVs) on CIFAR-10 classification task using VGG network. Our proposed cell holds potential for highly energy-efficient and error-tolerant BNNs on edge devices.