Modeling the Energy Consumption of Integrated Circuit Fab Infrastructure

Abstract

The bottom-up assessment of environmental impact of the fabrication of integrated circuit chips relies on accurate modeling of the operation of a high-volume semiconductor fab. In our virtual fab model, we structure fab operation in three concentric sectors: the wafer processing equipment, the generation of utilities that feeds the equipment, and the fab infrastructure that provides a suitable environment for the equipment and the workers. In this paper, we first address the correlation between process flow, wafer demand and fab dimension, which sets the scale of the virtual fab and enables global fab energy consumption estimates. Next, we describe how energy consumption calculations are performed sector-by-sector and how these evolve over the deployment of successive generations of logic nodes. In particular, we propose an original bottom-up model for fab infrastructure energy consumption that takes into account local climate dependence of a fab’s geographical location. The essence of these learnings is condensed into a normalized power consumption per manufacturing area (in kW/m2) that is deduced from our models as a function of technology maturity and location. These values form a good comparison basis with data from industry and literature.