{"title":"Exploring Sheet Thickness Scaling and Substrate Orientation for Maximizing Nanosheet pFET Performance","authors":"Ramandeep Kaur;Nihar R. Mohapatra","doi":"10.1109/TED.2024.3434775","DOIUrl":null,"url":null,"abstract":"We explored the performance of p-type nanosheet FETs (NsFETs) with sheet thickness scaling using a well-calibrated subband BTE solver that accounts for quantum confinement. Our investigation revealed that despite enhancements in gate electrostatics, the confined pFETs exhibit significantly reduced hole mobility due to increased phonon and surface roughness scattering (SRS). It is also found that introducing uniaxial compressive stress into the channel with an ideally flat surface (very low surface roughness) could boost the pFET on-current by approximately 2.5 times. Furthermore, by integrating p-type NsFETs on \n<inline-formula> <tex-math>$\\{ 110\\}$ </tex-math></inline-formula>\n substrate, rather than on conventional \n<inline-formula> <tex-math>$\\{ 100\\}$ </tex-math></inline-formula>\n substrate, it is likely to yield superior hole mobility and overall device performance, particularly at scaled sheet thicknesses.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9000,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10628019/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
We explored the performance of p-type nanosheet FETs (NsFETs) with sheet thickness scaling using a well-calibrated subband BTE solver that accounts for quantum confinement. Our investigation revealed that despite enhancements in gate electrostatics, the confined pFETs exhibit significantly reduced hole mobility due to increased phonon and surface roughness scattering (SRS). It is also found that introducing uniaxial compressive stress into the channel with an ideally flat surface (very low surface roughness) could boost the pFET on-current by approximately 2.5 times. Furthermore, by integrating p-type NsFETs on
$\{ 110\}$
substrate, rather than on conventional
$\{ 100\}$
substrate, it is likely to yield superior hole mobility and overall device performance, particularly at scaled sheet thicknesses.
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.