Bo Peng;Yaya Liang;Cong Liu;Ling Gao;Linjie Liu;Mingyang Wang;Zuoteng Gan;Pingan Du
{"title":"Design of Microchannels Embedded in HTCC Substrate for Heat Dissipation of SiP With Multiple Chips","authors":"Bo Peng;Yaya Liang;Cong Liu;Ling Gao;Linjie Liu;Mingyang Wang;Zuoteng Gan;Pingan Du","doi":"10.1109/TCPMT.2024.3438373","DOIUrl":null,"url":null,"abstract":"The escalating integration level of system-in-package (SiP) has brought about significant challenges in thermal management. To meet the requirements of ever-increasing heat flux of SiP system with multichips, a method of embedding cooling microchannels into high temperature co-fired ceramics (HTCCs) substrates is proposed in this article. First, five-microchannels embedded topology structure are designed to investigate their heat transfer performance in chip cooling in terms of the fluid-thermal coupling numerical simulations, and the results show that the spider-netted microchannel yields the best heat transfer performance, especially for the chip with high heat flux, and the conclusion that the spider-netted structure has superior heat dissipation is verified through experiments. Furthermore, a personalized spider-netted microchannel parallel structure relying the distribution of multichips heat flux is proposed to achieve efficient heat dissipation for SiP system, resulting in reduced chip temperatures and minimized interference from chips with high heat flux density on neighboring chips. Finally, a series of experiments are carried out to verify the feasibility of the designed microchannel structure for SiP. The research results indicate that embedding microchannels in HTCC substrates can be employed to improve the thermal dissipation capability of SiP and enhance chips integration.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3000,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10623226/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The escalating integration level of system-in-package (SiP) has brought about significant challenges in thermal management. To meet the requirements of ever-increasing heat flux of SiP system with multichips, a method of embedding cooling microchannels into high temperature co-fired ceramics (HTCCs) substrates is proposed in this article. First, five-microchannels embedded topology structure are designed to investigate their heat transfer performance in chip cooling in terms of the fluid-thermal coupling numerical simulations, and the results show that the spider-netted microchannel yields the best heat transfer performance, especially for the chip with high heat flux, and the conclusion that the spider-netted structure has superior heat dissipation is verified through experiments. Furthermore, a personalized spider-netted microchannel parallel structure relying the distribution of multichips heat flux is proposed to achieve efficient heat dissipation for SiP system, resulting in reduced chip temperatures and minimized interference from chips with high heat flux density on neighboring chips. Finally, a series of experiments are carried out to verify the feasibility of the designed microchannel structure for SiP. The research results indicate that embedding microchannels in HTCC substrates can be employed to improve the thermal dissipation capability of SiP and enhance chips integration.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.