Optimizing InGaAs/GaAsSb Staggered Bandgap U-Gate Line TFET With p+-Pocket Implant and Negative Capacitance for Enhanced Performance

IF 2.1 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Nanotechnology Pub Date : 2024-08-02 DOI:10.1109/TNANO.2024.3437669

Aadil Anam;S. Intekhab Amin;Dinesh Prasad

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引用次数: 0

Abstract

In this noteworthy paper, we present a novel and comprehensive investigation into the optimization of performance parameters for the conventional U-Gate III-V line TFET through TCAD simulation. Our unprecedented threefold optimization strategy encompasses multiple facets, marking a significant contribution to the field. Firstly, in our pursuit of enhancing OFF current performance, we implemented a pioneering approach by employing a highly doped p ⁺ -pocket, effectively suppressing parasitic corner tunneling and resulting in a remarkable 258.14-fold improvement in OFF current. Secondly, we embark on another unexplored avenue in conventional U-Gate TFET by implementing the negative capacitance (NC) effect into it. The NC implementation leads to substantial improvements in ON current and subthreshold swing (SS), with an impressive 4.176-fold enhancement in I _ON /I _OFF and a 2.151-fold reduction in average subthreshold swing (AVSS) (from 33.26 mV/dec to 15.46 mV/dec) compared to the conventional design. In the third and final stage of our optimization strategy, we efficiently combine the benefits of p ⁺ -pocket doping and NC implementation. By doing this, we simultaneously enhance the OFF current (improved by 226.91 times), ON current (improved by 1.92 times), I _ON /I _OFF ratio (enhanced by 435.55 times), and AVSS (improved by an outstanding 2.861 times, from 33.48 mV/dec to 11.7 mV/dec), demonstrating the effectiveness of our holistic approach. This comprehensive study sets a new benchmark for U-Gate III-V line TFET optimization, paving the way for advanced applications in low-power digital circuits.

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优化具有 p+ 凹槽植入和负电容的 InGaAs/GaAsSb 交错带隙 U 栅极线 TFET 以提高性能

在这篇值得关注的论文中，我们通过 TCAD 仿真对传统 U-Gate III-V 线路 TFET 性能参数的优化进行了新颖而全面的研究。我们前所未有的三重优化策略涵盖了多个方面，为该领域做出了重大贡献。首先，为了提高关断电流性能，我们开创性地采用了高掺杂 p+-pocket 方法，有效抑制了寄生角隧道效应，使关断电流显著提高了 258.14 倍。其次，我们在传统 U 栅极 TFET 中采用了负电容（NC）效应，从而开辟了另一条尚未探索的途径。实施 NC 后，导通电流和亚阈值摆幅（SS）都得到了大幅改善，与传统设计相比，ION/IOFF 增强了 4.176 倍，平均亚阈值摆幅（AVSS）降低了 2.151 倍（从 33.26 mV/dec 降至 15.46 mV/dec），令人印象深刻。在优化策略的第三阶段，也是最后阶段，我们有效地结合了 p+ pocket 掺杂和 NC 实现的优势。这样，我们同时提高了关断电流（提高了 226.91 倍）、导通电流（提高了 1.92 倍）、离子/离子交换比（提高了 435.55 倍）和 AVSS（提高了 2.861 倍，从 33.48 mV/dec 降至 11.7 mV/dec），证明了我们的整体方法的有效性。这项综合研究为 U-Gate III-V 线路 TFET 优化树立了新的标杆，为低功耗数字电路的先进应用铺平了道路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Nanotechnology 工程技术-材料科学：综合

CiteScore

4.80

自引率

8.30%

发文量

审稿时长

8.3 months

期刊介绍： The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.