Material Choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications

IF 4.1 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Lance Fernandes;Prasanna Venkatesan Ravindran;Taeyoung Song;Dipjyoti Das;Chinsung Park;Nashrah Afroze;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan
{"title":"Material Choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications","authors":"Lance Fernandes;Prasanna Venkatesan Ravindran;Taeyoung Song;Dipjyoti Das;Chinsung Park;Nashrah Afroze;Mengkun Tian;Hang Chen;Winston Chern;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Shimeng Yu;Suman Datta;Asif Khan","doi":"10.1109/LED.2024.3437239","DOIUrl":null,"url":null,"abstract":"We present an experimental study to compare the impacts of different dielectric materials - Al\n<sub>2</sub>\nO\n<sub>3</sub>\n and SiO\n<sub>2</sub>\n used as the tunnel dielectric layer (TDL) and the gate blocking layer (GBL) on the performance of ferroelectric gate stacks for NAND storage applications. We considered the maximum memory window (MW) and the incremental step program pulse (ISPP) slope as the key performance metrics. In a gate stack with TDL, Al\n<sub>2</sub>\nO\n<sub>3</sub>\n gives higher MW and ISPP performance than SiO\n<sub>2</sub>\n. However, in the GBL gate stack, SiO\n<sub>2</sub>\n has a higher MW and ISPP slope than Al\n<sub>2</sub>\nO\n<sub>3</sub>\n. With SiO\n<sub>2</sub>\n GBL, a maximum MW window of 8.3V was achieved, enabling quad-level cell (QLC) capability. We show that for a similar thickness, SiO\n<sub>2</sub>\n as GBL has the better MW performance, and Al\n<sub>2</sub>\nO\n<sub>3</sub>\n as TDL has a better ISPP performance. This study shows that TDL and GBL with appropriate dielectric material can be used as tuning knobs to achieve the desired ISPP and MW performance for ferroelectric NAND applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":null,"pages":null},"PeriodicalIF":4.1000,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10621062/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract

We present an experimental study to compare the impacts of different dielectric materials - Al 2 O 3 and SiO 2 used as the tunnel dielectric layer (TDL) and the gate blocking layer (GBL) on the performance of ferroelectric gate stacks for NAND storage applications. We considered the maximum memory window (MW) and the incremental step program pulse (ISPP) slope as the key performance metrics. In a gate stack with TDL, Al 2 O 3 gives higher MW and ISPP performance than SiO 2 . However, in the GBL gate stack, SiO 2 has a higher MW and ISPP slope than Al 2 O 3 . With SiO 2 GBL, a maximum MW window of 8.3V was achieved, enabling quad-level cell (QLC) capability. We show that for a similar thickness, SiO 2 as GBL has the better MW performance, and Al 2 O 3 as TDL has a better ISPP performance. This study shows that TDL and GBL with appropriate dielectric material can be used as tuning knobs to achieve the desired ISPP and MW performance for ferroelectric NAND applications.
铁电 NAND 应用中隧道介电层和栅极阻挡层的材料选择
我们进行了一项实验研究,比较了不同介电材料(Al2O3 和 SiO2)用作隧道介电层(TDL)和栅极阻挡层(GBL)对 NAND 存储应用中铁电栅极堆栈性能的影响。我们将最大存储窗口(MW)和增量阶跃程序脉冲(ISPP)斜率作为关键性能指标。在具有 TDL 的栅极堆栈中,Al2O3 的 MW 和 ISPP 性能均高于 SiO2。然而,在 GBL 栅极堆栈中,SiO2 的 MW 和 ISPP 斜坡均高于 Al2O3。使用二氧化硅 GBL 时,最大 MW 窗口可达 8.3V,从而实现了四电平电池 (QLC) 功能。我们发现,在厚度相似的情况下,SiO2 作为 GBL 具有更好的 MW 性能,而 Al2O3 作为 TDL 具有更好的 ISPP 性能。这项研究表明,采用适当介电材料的 TDL 和 GBL 可用作调谐旋钮,以实现铁电 NAND 应用所需的 ISPP 和 MW 性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Electron Device Letters
IEEE Electron Device Letters 工程技术-工程:电子与电气
CiteScore
8.20
自引率
10.20%
发文量
551
审稿时长
1.4 months
期刊介绍: IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.
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